_primary.vhd

来自「Viterbi decoder source code」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity conv_encoder7 is
    generic(
        wd_code          : integer := 2;
        constraint       : integer := 7
    );
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        x               : in     vl_logic;
        y               : out    vl_logic_vector
    );
end conv_encoder7;