_primary.vhd

来自「Viterbi decoder source code」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity apex20ke_jtag is
    generic(
        operation_mode   : string  := "input";
        input_mode       : string  := "none";
        output0_mode     : string  := "none";
        output1_mode     : string  := "none"
    );
    port(
        padio           : inout  vl_logic;
        datain          : in     vl_logic;
        dataout0        : out    vl_logic;
        dataout1        : out    vl_logic
    );
end apex20ke_jtag;