ram384x128.v

来自「Viterbi decoder source code」· Verilog 代码 · 共 29 行

module    RAM384X128  (   data,
                          addr, 
                          we,   
                          outen,
                          clock,
                          q    
                             );
    parameter   nobits = 128;

	input	[nobits-1:0]  data;
	input	[8:0]  	      addr;
	input	  		      we;
	input			      outen;
	input	 		      clock;
	output	[nobits-1:0]  q;

	// Empty
        reg [nobits-1:0] mem [383:0];
        reg [nobits-1:0] q;
        
        always@(posedge clock) begin
        	if(outen & !we)
        		q <= #1 mem[addr];
        	else if(!outen & we)
        		mem[addr] <= #1 data;
        end

endmodule