📄 viterbi_k7_inst.csf.msg
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{ Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"D:\\MyDocuments\\WLAN\\HDLcode\\Channel Decoder\\Viterbi1_0\\v1.1\\Synthesis\\SynplifyPrj\\rev_1\\viterbi_k7_inst.vqm\"
" "Verilog Design File information: Continuing analyzing of source file \"D:\\MyDocuments\\WLAN\\HDLcode\\Channel Decoder\\Viterbi1_0\\v1.1\\Synthesis\\SynplifyPrj\\rev_1\\viterbi_k7_inst.vqm\"
" { } { } }
{ Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"D:\\MyDocuments\\WLAN\\HDLcode\\Channel Decoder\\Viterbi1_0\\v1.1\\Synthesis\\SynplifyPrj\\rev_1\\viterbi_k7_inst.vqm\"
" "Verilog Design File information: Continuing analyzing of source file \"D:\\MyDocuments\\WLAN\\HDLcode\\Channel Decoder\\Viterbi1_0\\v1.1\\Synthesis\\SynplifyPrj\\rev_1\\viterbi_k7_inst.vqm\"
" { } { } }
{ Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"D:\\MyDocuments\\WLAN\\HDLcode\\Channel Decoder\\Viterbi1_0\\v1.1\\Synthesis\\SynplifyPrj\\rev_1\\viterbi_k7_inst.vqm\"
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