seqdet2.map.qmsg

状态机实现序列检测VerilogHDL及其仿真

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 22 16:38:08 2009 " "Info: Processing started: Sun Feb 22 16:38:08 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off seqdet2 -c seqdet2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off seqdet2 -c seqdet2" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seqdet2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file seqdet2.v" { { "Info" "ISGN_ENTITY_NAME" "1 seqdet2 " "Info: Found entity 1: seqdet2" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "seqdet2 " "Info: Elaborating entity \"seqdet2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 seqdet2.v(20) " "Warning (10230): Verilog HDL assignment warning at seqdet2.v(20): truncated value with size 32 to match size of target (1)" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|seqdet2\|state 13 " "Info: State machine \"\|seqdet2\|state\" contains 13 states" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|seqdet2\|state " "Info: Selected Auto state machine encoding method for state machine \"\|seqdet2\|state\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|seqdet2\|state " "Info: Encoding result for state machine \"\|seqdet2\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "13 " "Info: Completed encoding using 13 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.H " "Info: Encoded state bit \"state.H\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.L " "Info: Encoded state bit \"state.L\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.A " "Info: Encoded state bit \"state.A\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.B " "Info: Encoded state bit \"state.B\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.J " "Info: Encoded state bit \"state.J\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.C " "Info: Encoded state bit \"state.C\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.K " "Info: Encoded state bit \"state.K\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.D " "Info: Encoded state bit \"state.D\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.E " "Info: Encoded state bit \"state.E\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.F " "Info: Encoded state bit \"state.F\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.G " "Info: Encoded state bit \"state.G\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.I " "Info: Encoded state bit \"state.I\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.IDLE " "Info: Encoded state bit \"state.IDLE\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|seqdet2\|state.IDLE 0000000000000 " "Info: State \"\|seqdet2\|state.IDLE\" uses code string \"0000000000000\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|seqdet2\|state.I 0000000000011 " "Info: State \"\|seqdet2\|state.I\" uses code string \"0000000000011\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|seqdet2\|state.G 0000000000101 " "Info: State \"\|seqdet2\|state.G\" uses code string \"0000000000101\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|seqdet2\|state.F 0000000001001 " "Info: State \"\|seqdet2\|state.F\" uses code string \"0000000001001\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|seqdet2\|state.E 0000000010001 " "Info: State \"\|seqdet2\|state.E\" uses code string \"0000000010001\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|seqdet2\|state.D 0000000100001 " "Info: State \"\|seqdet2\|state.D\" uses code string \"0000000100001\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|seqdet2\|state.K 0000001000001 " "Info: State \"\|seqdet2\|state.K\" uses code string \"0000001000001\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|seqdet2\|state.C 0000010000001 " "Info: State \"\|seqdet2\|state.C\" uses code string \"0000010000001\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|seqdet2\|state.J 0000100000001 " "Info: State \"\|seqdet2\|state.J\" uses code string \"0000100000001\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|seqdet2\|state.B 0001000000001 " "Info: State \"\|seqdet2\|state.B\" uses code string \"0001000000001\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|seqdet2\|state.A 0010000000001 " "Info: State \"\|seqdet2\|state.A\" uses code string \"0010000000001\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|seqdet2\|state.L 0100000000001 " "Info: State \"\|seqdet2\|state.L\" uses code string \"0100000000001\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|seqdet2\|state.H 1000000000001 " "Info: State \"\|seqdet2\|state.H\" uses code string \"1000000000001\"" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "19 " "Info: Implemented 19 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "15 " "Info: Implemented 15 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 22 16:38:10 2009 " "Info: Processing ended: Sun Feb 22 16:38:10 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}