seqdet2.hier_info

状态机实现序列检测VerilogHDL及其仿真

|seqdet2
z <= z~0.DB_MAX_OUTPUT_PORT_TYPE
x => z~0.IN1
x => Selector1.IN0
x => state~1.DATAB
x => Selector3.IN1
x => state~0.DATAB
x => Selector4.IN1
x => state~2.DATAB
x => state~3.DATAB
x => state~4.DATAB
x => state~5.DATAB
x => Selector2.IN1
x => state~6.DATAB
x => Selector0.IN1
x => Selector5.IN1
clk => state~7.IN1
rst => state~8.IN1