seqdet2.tan.qmsg

状态机实现序列检测VerilogHDL及其仿真

{ "Info" "ITDB_TH_RESULT" "state.K x clk -1.593 ns register " "Info: th for register \"state.K\" (data pin = \"x\", clock pin = \"clk\") is -1.593 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.009 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 13 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 13; CLK Node = 'clk'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.639 ns) + CELL(0.542 ns) 3.009 ns state.K 2 REG LC_X1_Y1_N1 2 " "Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X1_Y1_N1; Fanout = 2; REG Node = 'state.K'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.181 ns" { clk state.K } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.53 % ) " "Info: Total cell delay = 1.370 ns ( 45.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.639 ns ( 54.47 % ) " "Info: Total interconnect delay = 1.639 ns ( 54.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk state.K } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 state.K } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.702 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.702 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns x 1 PIN PIN_U20 14 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_U20; Fanout = 14; PIN Node = 'x'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { x } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.245 ns) + CELL(0.223 ns) 4.702 ns state.K 2 REG LC_X1_Y1_N1 2 " "Info: 2: + IC(3.245 ns) + CELL(0.223 ns) = 4.702 ns; Loc. = LC_X1_Y1_N1; Fanout = 2; REG Node = 'state.K'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.468 ns" { x state.K } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns ( 30.99 % ) " "Info: Total cell delay = 1.457 ns ( 30.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.245 ns ( 69.01 % ) " "Info: Total interconnect delay = 3.245 ns ( 69.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "4.702 ns" { x state.K } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "4.702 ns" { x x~out0 state.K } { 0.000ns 0.000ns 3.245ns } { 0.000ns 1.234ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk state.K } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 state.K } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "4.702 ns" { x state.K } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "4.702 ns" { x x~out0 state.K } { 0.000ns 0.000ns 3.245ns } { 0.000ns 1.234ns 0.223ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 22 16:39:13 2009 " "Info: Processing ended: Sun Feb 22 16:39:13 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}