seqdet2.tan.qmsg

状态机实现序列检测VerilogHDL及其仿真

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register state.IDLE state.A 422.12 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 422.12 MHz between source register \"state.IDLE\" and destination register \"state.A\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.116 ns + Longest register register " "Info: + Longest register to register delay is 1.116 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.IDLE 1 REG LC_X1_Y1_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y1_N7; Fanout = 2; REG Node = 'state.IDLE'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { state.IDLE } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.393 ns) + CELL(0.366 ns) 0.759 ns Selector4~40 2 COMB LC_X1_Y1_N3 1 " "Info: 2: + IC(0.393 ns) + CELL(0.366 ns) = 0.759 ns; Loc. = LC_X1_Y1_N3; Fanout = 1; COMB Node = 'Selector4~40'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "0.759 ns" { state.IDLE Selector4~40 } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.134 ns) + CELL(0.223 ns) 1.116 ns state.A 3 REG LC_X1_Y1_N4 2 " "Info: 3: + IC(0.134 ns) + CELL(0.223 ns) = 1.116 ns; Loc. = LC_X1_Y1_N4; Fanout = 2; REG Node = 'state.A'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "0.357 ns" { Selector4~40 state.A } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.589 ns ( 52.78 % ) " "Info: Total cell delay = 0.589 ns ( 52.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.527 ns ( 47.22 % ) " "Info: Total interconnect delay = 0.527 ns ( 47.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "1.116 ns" { state.IDLE Selector4~40 state.A } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "1.116 ns" { state.IDLE Selector4~40 state.A } { 0.000ns 0.393ns 0.134ns } { 0.000ns 0.366ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.009 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 13 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 13; CLK Node = 'clk'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.639 ns) + CELL(0.542 ns) 3.009 ns state.A 2 REG LC_X1_Y1_N4 2 " "Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X1_Y1_N4; Fanout = 2; REG Node = 'state.A'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.181 ns" { clk state.A } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.53 % ) " "Info: Total cell delay = 1.370 ns ( 45.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.639 ns ( 54.47 % ) " "Info: Total interconnect delay = 1.639 ns ( 54.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk state.A } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 state.A } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.009 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 13 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 13; CLK Node = 'clk'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.639 ns) + CELL(0.542 ns) 3.009 ns state.IDLE 2 REG LC_X1_Y1_N7 2 " "Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X1_Y1_N7; Fanout = 2; REG Node = 'state.IDLE'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.181 ns" { clk state.IDLE } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.53 % ) " "Info: Total cell delay = 1.370 ns ( 45.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.639 ns ( 54.47 % ) " "Info: Total interconnect delay = 1.639 ns ( 54.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk state.IDLE } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 state.IDLE } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk state.A } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 state.A } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk state.IDLE } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 state.IDLE } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "1.116 ns" { state.IDLE Selector4~40 state.A } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "1.116 ns" { state.IDLE Selector4~40 state.A } { 0.000ns 0.393ns 0.134ns } { 0.000ns 0.366ns 0.223ns } } } { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk state.A } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 state.A } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk state.IDLE } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 state.IDLE } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { state.A } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { state.A } {  } {  } } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "state.C x clk 2.298 ns register " "Info: tsu for register \"state.C\" (data pin = \"x\", clock pin = \"clk\") is 2.298 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.297 ns + Longest pin register " "Info: + Longest pin to register delay is 5.297 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns x 1 PIN PIN_U20 14 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_U20; Fanout = 14; PIN Node = 'x'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { x } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.524 ns) + CELL(0.539 ns) 5.297 ns state.C 2 REG LC_X2_Y1_N6 2 " "Info: 2: + IC(3.524 ns) + CELL(0.539 ns) = 5.297 ns; Loc. = LC_X2_Y1_N6; Fanout = 2; REG Node = 'state.C'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "4.063 ns" { x state.C } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.773 ns ( 33.47 % ) " "Info: Total cell delay = 1.773 ns ( 33.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.524 ns ( 66.53 % ) " "Info: Total interconnect delay = 3.524 ns ( 66.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "5.297 ns" { x state.C } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "5.297 ns" { x x~out0 state.C } { 0.000ns 0.000ns 3.524ns } { 0.000ns 1.234ns 0.539ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.009 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 13 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 13; CLK Node = 'clk'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.639 ns) + CELL(0.542 ns) 3.009 ns state.C 2 REG LC_X2_Y1_N6 2 " "Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X2_Y1_N6; Fanout = 2; REG Node = 'state.C'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.181 ns" { clk state.C } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.53 % ) " "Info: Total cell delay = 1.370 ns ( 45.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.639 ns ( 54.47 % ) " "Info: Total interconnect delay = 1.639 ns ( 54.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk state.C } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 state.C } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "5.297 ns" { x state.C } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "5.297 ns" { x x~out0 state.C } { 0.000ns 0.000ns 3.524ns } { 0.000ns 1.234ns 0.539ns } } } { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk state.C } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 state.C } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk z state.H 6.781 ns register " "Info: tco from clock \"clk\" to destination pin \"z\" through register \"state.H\" is 6.781 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.009 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 13 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 13; CLK Node = 'clk'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.639 ns) + CELL(0.542 ns) 3.009 ns state.H 2 REG LC_X1_Y1_N0 3 " "Info: 2: + IC(1.639 ns) + CELL(0.542 ns) = 3.009 ns; Loc. = LC_X1_Y1_N0; Fanout = 3; REG Node = 'state.H'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "2.181 ns" { clk state.H } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.53 % ) " "Info: Total cell delay = 1.370 ns ( 45.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.639 ns ( 54.47 % ) " "Info: Total interconnect delay = 1.639 ns ( 54.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk state.H } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 state.H } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.616 ns + Longest register pin " "Info: + Longest register to pin delay is 3.616 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.H 1 REG LC_X1_Y1_N0 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y1_N0; Fanout = 3; REG Node = 'state.H'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { state.H } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.413 ns) + CELL(0.075 ns) 0.488 ns z~0 2 COMB LC_X1_Y1_N6 1 " "Info: 2: + IC(0.413 ns) + CELL(0.075 ns) = 0.488 ns; Loc. = LC_X1_Y1_N6; Fanout = 1; COMB Node = 'z~0'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "0.488 ns" { state.H z~0 } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(2.376 ns) 3.616 ns z 3 PIN PIN_U19 0 " "Info: 3: + IC(0.752 ns) + CELL(2.376 ns) = 3.616 ns; Loc. = PIN_U19; Fanout = 0; PIN Node = 'z'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.128 ns" { z~0 z } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.451 ns ( 67.78 % ) " "Info: Total cell delay = 2.451 ns ( 67.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.165 ns ( 32.22 % ) " "Info: Total interconnect delay = 1.165 ns ( 32.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.616 ns" { state.H z~0 z } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "3.616 ns" { state.H z~0 z } { 0.000ns 0.413ns 0.752ns } { 0.000ns 0.075ns 2.376ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.009 ns" { clk state.H } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "3.009 ns" { clk clk~out0 state.H } { 0.000ns 0.000ns 1.639ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.616 ns" { state.H z~0 z } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "3.616 ns" { state.H z~0 z } { 0.000ns 0.413ns 0.752ns } { 0.000ns 0.075ns 2.376ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "x z 7.884 ns Longest " "Info: Longest tpd from source pin \"x\" to destination pin \"z\" is 7.884 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns x 1 PIN PIN_U20 14 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_U20; Fanout = 14; PIN Node = 'x'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "" { x } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.242 ns) + CELL(0.280 ns) 4.756 ns z~0 2 COMB LC_X1_Y1_N6 1 " "Info: 2: + IC(3.242 ns) + CELL(0.280 ns) = 4.756 ns; Loc. = LC_X1_Y1_N6; Fanout = 1; COMB Node = 'z~0'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.522 ns" { x z~0 } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(2.376 ns) 7.884 ns z 3 PIN PIN_U19 0 " "Info: 3: + IC(0.752 ns) + CELL(2.376 ns) = 7.884 ns; Loc. = PIN_U19; Fanout = 0; PIN Node = 'z'" {  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "3.128 ns" { z~0 z } "NODE_NAME" } } { "seqdet2.v" "" { Text "D:/alter/quartusII/newprojec/seqdet2/seqdet2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.890 ns ( 49.34 % ) " "Info: Total cell delay = 3.890 ns ( 49.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.994 ns ( 50.66 % ) " "Info: Total interconnect delay = 3.994 ns ( 50.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/alter/quartusii/win/TimingClosureFloorplan.fld" "" "7.884 ns" { x z~0 z } "NODE_NAME" } } { "d:/alter/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/alter/quartusii/win/Technology_Viewer.qrui" "7.884 ns" { x x~out0 z~0 z } { 0.000ns 0.000ns 3.242ns 0.752ns } { 0.000ns 1.234ns 0.280ns 2.376ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}