seqdet2.qsf

状态机实现序列检测VerilogHDL及其仿真

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		seqdet2_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Stratix
set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY seqdet2
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:31:35  FEBRUARY 22, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "Active-HDL (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "PrimeTime (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_timing_analysis
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
set_global_assignment -name VERILOG_FILE "D:\\alter\\quartusII\\newprojec\\seqdet2\\seqdet2.v"
set_global_assignment -name VECTOR_WAVEFORM_FILE seqdet2.vwf
set_global_assignment -name SIMULATION_MODE FUNCTIONAL