seqdet2.map.summary

来自「状态机实现序列检测VerilogHDL及其仿真」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Sun Feb 22 16:38:10 2009
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : seqdet2
Top-level Entity Name : seqdet2
Family : Stratix
Total logic elements : 15
Total pins : 4
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0