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📄 seqdet2_v.sdo

📁 状态机实现序列检测VerilogHDL及其仿真
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    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE state\.A\~I.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (856:856:856) (856:856:856))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE state\.A\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2287:2287:2287) (2287:2287:2287))
        (PORT clk (2181:2181:2181) (2181:2181:2181))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE state\.B\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (399:399:399) (399:399:399))
        (PORT datab (3236:3236:3236) (3236:3236:3236))
        (PORT datac (555:555:555) (555:555:555))
        (PORT datad (411:411:411) (411:411:411))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE state\.B\~I.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (874:874:874) (874:874:874))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE state\.B\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2287:2287:2287) (2287:2287:2287))
        (PORT clk (2181:2181:2181) (2181:2181:2181))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE state\.C\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (3524:3524:3524) (3524:3524:3524))
        (PORT datab (389:389:389) (389:389:389))
        (PORT datad (528:528:528) (528:528:528))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE state\.C\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2287:2287:2287) (2287:2287:2287))
        (PORT clk (2181:2181:2181) (2181:2181:2181))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE state\.D\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (3518:3518:3518) (3518:3518:3518))
        (PORT datad (403:403:403) (403:403:403))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE state\.D\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2287:2287:2287) (2287:2287:2287))
        (PORT clk (2181:2181:2181) (2181:2181:2181))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE state\.E\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (386:386:386) (386:386:386))
        (PORT datad (3510:3510:3510) (3510:3510:3510))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE state\.E\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2287:2287:2287) (2287:2287:2287))
        (PORT clk (2181:2181:2181) (2181:2181:2181))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE state\.F\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (398:398:398) (398:398:398))
        (PORT datad (3512:3512:3512) (3512:3512:3512))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE state\.F\~I.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (717:717:717) (717:717:717))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE state\.F\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2287:2287:2287) (2287:2287:2287))
        (PORT clk (2181:2181:2181) (2181:2181:2181))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE state\.G\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (3241:3241:3241) (3241:3241:3241))
        (PORT datad (538:538:538) (538:538:538))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE state\.G\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2287:2287:2287) (2287:2287:2287))
        (PORT clk (2181:2181:2181) (2181:2181:2181))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE state\.H\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (556:556:556) (556:556:556))
        (PORT datad (3246:3246:3246) (3246:3246:3246))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE state\.H\~I.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (875:875:875) (875:875:875))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE state\.H\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2287:2287:2287) (2287:2287:2287))
        (PORT clk (2181:2181:2181) (2181:2181:2181))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE z\~I.inst1)
    (DELAY
      (ABSOLUTE
        (PORT datain (752:752:752) (752:752:752))
        (IOPATH datain padio (2376:2376:2376) (2376:2376:2376))
      )
    )
  )
)

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