seqdet2_v.sdo

状态机实现序列检测VerilogHDL及其仿真

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP1S10F484C5 Package FBGA484
// 

// 
// This SDF file should be used for PrimeTime (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "seqdet2")
  (DATE "02/22/2009 16:39:17")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE clk\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (828:828:828) (828:828:828))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE x\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (1234:1234:1234) (1234:1234:1234))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io")
    (INSTANCE rst\~I.inst1)
    (DELAY
      (ABSOLUTE
        (IOPATH padio combout (725:725:725) (725:725:725))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE state\.K\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (399:399:399) (399:399:399))
        (PORT datad (3245:3245:3245) (3245:3245:3245))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE state\.K\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2287:2287:2287) (2287:2287:2287))
        (PORT clk (2181:2181:2181) (2181:2181:2181))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE state\.I\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (3242:3242:3242) (3242:3242:3242))
        (PORT datad (413:413:413) (413:413:413))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH datad regin (223:223:223) (223:223:223))
        (IOPATH datab combout (280:280:280) (280:280:280))
        (IOPATH datad combout (75:75:75) (75:75:75))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE state\.I\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2287:2287:2287) (2287:2287:2287))
        (PORT clk (2181:2181:2181) (2181:2181:2181))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE state\.J\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (3241:3241:3241) (3241:3241:3241))
        (PORT datac (526:526:526) (526:526:526))
        (PORT datad (408:408:408) (408:408:408))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE state\.J\~I.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (845:845:845) (845:845:845))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE state\.J\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2287:2287:2287) (2287:2287:2287))
        (PORT clk (2181:2181:2181) (2181:2181:2181))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE state\.L\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (3492:3492:3492) (3492:3492:3492))
        (PORT datab (401:401:401) (401:401:401))
        (PORT datac (535:535:535) (535:535:535))
        (PORT datad (414:414:414) (414:414:414))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE state\.L\~I.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (854:854:854) (854:854:854))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE state\.L\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2287:2287:2287) (2287:2287:2287))
        (PORT clk (2181:2181:2181) (2181:2181:2181))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE state\.IDLE\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (3490:3490:3490) (3490:3490:3490))
        (PORT datab (396:396:396) (396:396:396))
        (PORT datac (549:549:549) (549:549:549))
        (PORT datad (539:539:539) (539:539:539))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE state\.IDLE\~I.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (868:868:868) (868:868:868))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_lcell_register")
    (INSTANCE state\.IDLE\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2287:2287:2287) (2287:2287:2287))
        (PORT clk (2181:2181:2181) (2181:2181:2181))
        (IOPATH (posedge clk) regout (156:156:156) (156:156:156))
        (IOPATH (posedge aclr) regout (176:176:176) (176:176:176))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (10:10:10))
      (HOLD datain (posedge clk) (100:100:100))
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE Selector4\~40_I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (393:393:393) (393:393:393))
        (PORT datab (400:400:400) (400:400:400))
        (PORT datac (425:425:425) (425:425:425))
        (PORT datad (397:397:397) (397:397:397))
        (IOPATH dataa combout (366:366:366) (366:366:366))
        (IOPATH datab combout (280:280:280) (280:280:280))
        (IOPATH datac combout (183:183:183) (183:183:183))
        (IOPATH datad combout (75:75:75) (75:75:75))
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_lcell")
    (INSTANCE state\.A\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (3488:3488:3488) (3488:3488:3488))
        (PORT datab (510:510:510) (510:510:510))
        (PORT datac (537:537:537) (537:537:537))
        (PORT datad (134:134:134) (134:134:134))
        (IOPATH dataa regin (539:539:539) (539:539:539))
        (IOPATH datab regin (458:458:458) (458:458:458))
        (IOPATH datad regin (223:223:223) (223:223:223))
      )