seqdet2.v

状态机实现序列检测VerilogHDL及其仿真

module seqdet2(z,x,clk,rst);
output z;
input x,clk,rst;
reg[3:0] state;
wire z;

parameter IDLE=4'b0,
          A=4'd1,
          B=4'd2,
          C=4'd3,
          D=4'd4,
          E=4'd5,
          F=4'd6,
          G=4'd7,
          H=4'd8,
          I=4'd9,
          J=4'd10,
          K=4'd11,
          L=4'd12;
assign z=(state==H&&x==1)?1:0;

always @(posedge clk or negedge rst)
  if(!rst)
    begin
     state<=IDLE;
    end
else
   case(state)
IDLE:if(x==1)
       state<=A;
       else
     state<=IDLE;
A:if(x==1)
   state<=B;
  else
   state<=J;
B:if(x==1)
  state<=C;
  else
  state<=K;
C:if(x==0)
   state<=D;
 else
  state<=C;
D:if(x==0)
   state<=E;
   else 
 state<=A;
E:if(x==0)
  state<=F;
  else
 state<=A;
F:if(x==1)
  state<=G;
  else
  state<=IDLE;
G:if(x==0)
   state<=H;
  else
  state<=B;
H:if(x==1)
  state<=I;
 else
  state<=L;
I:if(x==0)
   state<=J;
  else
 state<=B;
J:if(x==0)
  state<=L;
  else
   state<=A;
K:if(x==0)
   state<=L;
   else
  state<=A;
L:if(x==1)
  state<=A;
  else
  state<=IDLE;
default:state<=IDLE;

  endcase
endmodule