seqdet2.vo

状态机实现序列检测VerilogHDL及其仿真

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

// DATE "02/22/2009 16:39:17"

// 
// Device: Altera EP1S10F484C5 Package FBGA484
// 

// 
// This Verilog file should be used for Active-HDL (Verilog) only
// 

`timescale 1 ps/ 1 ps

module seqdet2 (
	z,
	x,
	clk,
	rst);
output 	z;
input 	x;
input 	clk;
input 	rst;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("seqdet2_v.sdo");
// synopsys translate_on

wire \clk~combout ;
wire \x~combout ;
wire \rst~combout ;
wire \state.K ;
wire \state.I ;
wire \state.J ;
wire \state.L ;
wire \state.IDLE ;
wire \Selector4~40 ;
wire \state.A ;
wire \state.B ;
wire \state.C ;
wire \state.D ;
wire \state.E ;
wire \state.F ;
wire \state.G ;
wire \state.H ;
wire \z~0 ;


// atom is at PIN_M20
stratix_io \clk~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clk~combout ),
	.regout(),
	.ddioregout(),
	.padio(clk),
	.dqsundelayedout());
// synopsys translate_off
defparam \clk~I .ddio_mode = "none";
defparam \clk~I .input_async_reset = "none";
defparam \clk~I .input_power_up = "low";
defparam \clk~I .input_register_mode = "none";
defparam \clk~I .input_sync_reset = "none";
defparam \clk~I .oe_async_reset = "none";
defparam \clk~I .oe_power_up = "low";
defparam \clk~I .oe_register_mode = "none";
defparam \clk~I .oe_sync_reset = "none";
defparam \clk~I .operation_mode = "input";
defparam \clk~I .output_async_reset = "none";
defparam \clk~I .output_power_up = "low";
defparam \clk~I .output_register_mode = "none";
defparam \clk~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_U20
stratix_io \x~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\x~combout ),
	.regout(),
	.ddioregout(),
	.padio(x),
	.dqsundelayedout());
// synopsys translate_off
defparam \x~I .ddio_mode = "none";
defparam \x~I .input_async_reset = "none";
defparam \x~I .input_power_up = "low";
defparam \x~I .input_register_mode = "none";
defparam \x~I .input_sync_reset = "none";
defparam \x~I .oe_async_reset = "none";
defparam \x~I .oe_power_up = "low";
defparam \x~I .oe_register_mode = "none";
defparam \x~I .oe_sync_reset = "none";
defparam \x~I .operation_mode = "input";
defparam \x~I .output_async_reset = "none";
defparam \x~I .output_power_up = "low";
defparam \x~I .output_register_mode = "none";
defparam \x~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_M21
stratix_io \rst~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rst~combout ),
	.regout(),
	.ddioregout(),
	.padio(rst),
	.dqsundelayedout());
// synopsys translate_off
defparam \rst~I .ddio_mode = "none";
defparam \rst~I .input_async_reset = "none";
defparam \rst~I .input_power_up = "low";
defparam \rst~I .input_register_mode = "none";
defparam \rst~I .input_sync_reset = "none";
defparam \rst~I .oe_async_reset = "none";
defparam \rst~I .oe_power_up = "low";
defparam \rst~I .oe_register_mode = "none";
defparam \rst~I .oe_sync_reset = "none";
defparam \rst~I .operation_mode = "input";
defparam \rst~I .output_async_reset = "none";
defparam \rst~I .output_power_up = "low";
defparam \rst~I .output_register_mode = "none";
defparam \rst~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X1_Y1_N1
stratix_lcell \state.K~I (
// Equation(s):
// \state.K  = DFFEAS(\state.B  & (!\x~combout ), GLOBAL(\clk~combout ), GLOBAL(\rst~combout ), , , , , , )

	.clk(\clk~combout ),
	.dataa(\state.B ),
	.datab(vcc),
	.datac(vcc),
	.datad(\x~combout ),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\state.K ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \state.K~I .lut_mask = "00AA";
defparam \state.K~I .operation_mode = "normal";
defparam \state.K~I .output_mode = "reg_only";
defparam \state.K~I .register_cascade_mode = "off";
defparam \state.K~I .sum_lutc_input = "datac";
defparam \state.K~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X1_Y1_N6
stratix_lcell \state.I~I (
// Equation(s):
// \z~0  = \x~combout  & (\state.H )
// \state.I  = DFFEAS(\z~0 , GLOBAL(\clk~combout ), GLOBAL(\rst~combout ), , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(\x~combout ),
	.datac(vcc),
	.datad(\state.H ),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\z~0 ),
	.regout(\state.I ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \state.I~I .lut_mask = "CC00";
defparam \state.I~I .operation_mode = "normal";
defparam \state.I~I .output_mode = "reg_and_comb";
defparam \state.I~I .register_cascade_mode = "off";
defparam \state.I~I .sum_lutc_input = "datac";
defparam \state.I~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X1_Y1_N9
stratix_lcell \state.J~I (
// Equation(s):
// \state.J  = DFFEAS(!\x~combout  & (\state.A  # \state.I ), GLOBAL(\clk~combout ), GLOBAL(\rst~combout ), , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(\x~combout ),
	.datac(\state.A ),
	.datad(\state.I ),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\state.J ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \state.J~I .lut_mask = "3330";
defparam \state.J~I .operation_mode = "normal";
defparam \state.J~I .output_mode = "reg_only";
defparam \state.J~I .register_cascade_mode = "off";
defparam \state.J~I .sum_lutc_input = "datac";
defparam \state.J~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X1_Y1_N5
stratix_lcell \state.L~I (
// Equation(s):
// \state.L  = DFFEAS(!\x~combout  & (\state.K  # \state.J  # \state.H ), GLOBAL(\clk~combout ), GLOBAL(\rst~combout ), , , , , , )

	.clk(\clk~combout ),
	.dataa(\x~combout ),
	.datab(\state.K ),
	.datac(\state.J ),
	.datad(\state.H ),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\state.L ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \state.L~I .lut_mask = "5554";
defparam \state.L~I .operation_mode = "normal";
defparam \state.L~I .output_mode = "reg_only";
defparam \state.L~I .register_cascade_mode = "off";
defparam \state.L~I .sum_lutc_input = "datac";
defparam \state.L~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X1_Y1_N7
stratix_lcell \state.IDLE~I (
// Equation(s):
// \state.IDLE  = DFFEAS(\x~combout  # !\state.L  & \state.IDLE  & !\state.F , GLOBAL(\clk~combout ), GLOBAL(\rst~combout ), , , , , , )

	.clk(\clk~combout ),
	.dataa(\x~combout ),
	.datab(\state.L ),
	.datac(\state.IDLE ),
	.datad(\state.F ),
	.aclr(!\rst~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\state.IDLE ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \state.IDLE~I .lut_mask = "AABA";
defparam \state.IDLE~I .operation_mode = "normal";
defparam \state.IDLE~I .output_mode = "reg_only";
defparam \state.IDLE~I .register_cascade_mode = "off";
defparam \state.IDLE~I .sum_lutc_input = "datac";
defparam \state.IDLE~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X1_Y1_N3