seqdet2.eda.rpt

状态机实现序列检测VerilogHDL及其仿真

EDA Netlist Writer report for seqdet2
Sun Feb 22 16:39:17 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. EDA Netlist Writer Summary
  3. Simulation Settings
  4. Simulation Generated Files
  5. Timing Analysis Settings
  6. Timing Analysis Generated Files
  7. EDA Netlist Writer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; EDA Netlist Writer Summary                                             ;
+--------------------------------+---------------------------------------+
; EDA Netlist Writer Status      ; Successful - Sun Feb 22 16:39:17 2009 ;
; Revision Name                  ; seqdet2                               ;
; Top-level Entity Name          ; seqdet2                               ;
; Family                         ; Stratix                               ;
; Simulation Files Creation      ; Successful                            ;
; Timing Analysis Files Creation ; Successful                            ;
+--------------------------------+---------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Simulation Settings                                                                                               ;
+--------------------------------------------------------------------------------------------+----------------------+
; Option                                                                                     ; Setting              ;
+--------------------------------------------------------------------------------------------+----------------------+
; Tool Name                                                                                  ; Active-HDL (Verilog) ;
; Generate netlist for functional simulation only                                            ; Off                  ;
; Time scale                                                                                 ; 1 ps                 ;
; Truncate long hierarchy paths                                                              ; Off                  ;
; Map illegal HDL characters                                                                 ; Off                  ;
; Flatten buses into individual nodes                                                        ; Off                  ;
; Maintain hierarchy                                                                         ; Off                  ;
; Bring out device-wide set/reset signals as ports                                           ; Off                  ;
; Enable glitch filtering                                                                    ; Off                  ;
; Do not write top level VHDL entity                                                         ; Off                  ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off                  ;
; Architecture name in VHDL output netlist                                                   ; structure            ;
+--------------------------------------------------------------------------------------------+----------------------+


+-------------------------------------------------------------------------+
; Simulation Generated Files                                              ;
+-------------------------------------------------------------------------+
; Generated Files                                                         ;
+-------------------------------------------------------------------------+
; D:/alter/quartusII/newprojec/seqdet2/simulation/activehdl/seqdet2.vo    ;
; D:/alter/quartusII/newprojec/seqdet2/simulation/activehdl/seqdet2_v.sdo ;
+-------------------------------------------------------------------------+


+-----------------------------------------------------------+
; Timing Analysis Settings                                  ;
+-------------------------------------+---------------------+
; Option                              ; Setting             ;
+-------------------------------------+---------------------+
; Tool Name                           ; PrimeTime (Verilog) ;
; Time scale                          ; 1 ps                ;
; Truncate long hierarchy paths       ; Off                 ;
; Map illegal HDL characters          ; Off                 ;
; Flatten buses into individual nodes ; Off                 ;
+-------------------------------------+---------------------+


+------------------------------------------------------------------------+
; Timing Analysis Generated Files                                        ;
+------------------------------------------------------------------------+
; Generated Files                                                        ;
+------------------------------------------------------------------------+
; D:/alter/quartusII/newprojec/seqdet2/timing/primetime/seqdet2.vo       ;
; D:/alter/quartusII/newprojec/seqdet2/timing/primetime/seqdet2_v.sdo    ;
; D:/alter/quartusII/newprojec/seqdet2/timing/primetime/seqdet2_pt_v.tcl ;
+------------------------------------------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II EDA Netlist Writer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Feb 22 16:39:16 2009
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off seqdet2 -c seqdet2
Info: Generated files "seqdet2.vo" and "seqdet2_v.sdo" in directory "D:/alter/quartusII/newprojec/seqdet2/simulation/activehdl/" for EDA simulation tool
Info: Generated files "seqdet2.vo" and "seqdet2_v.sdo" in directory "D:/alter/quartusII/newprojec/seqdet2/timing/primetime/" for EDA timing analysis tool
Info: Generated PrimeTime Tcl script file D:/alter/quartusII/newprojec/seqdet2/timing/primetime/seqdet2_pt_v.tcl
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
    Info: Processing ended: Sun Feb 22 16:39:17 2009
    Info: Elapsed time: 00:00:02