⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 prev_cmp_uart.map.qmsg

📁 FPGA的串口模块
💻 QMSG
📖 第 1 页 / 共 2 页
字号:
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "transfer:inst2\|lpm_add_sub:Add1 " "Info: Instantiated megafunction \"transfer:inst2\|lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 32 " "Info: Parameter \"LPM_WIDTH\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 43 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../72/quartus/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../72/quartus/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "transfer:inst2\|lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:oflow_node transfer:inst2\|lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"transfer:inst2\|lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"transfer:inst2\|lpm_add_sub:Add1\"" {  } { { "addcore.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } } { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 43 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "transfer:inst2\|lpm_add_sub:Add1 " "Info: Instantiated megafunction \"transfer:inst2\|lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 32 " "Info: Parameter \"LPM_WIDTH\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 43 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "transfer:inst2\|lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:result_node transfer:inst2\|lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"transfer:inst2\|lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"transfer:inst2\|lpm_add_sub:Add1\"" {  } { { "addcore.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/addcore.tdf" 123 6 0 } } { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 43 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "transfer:inst2\|lpm_add_sub:Add1 " "Info: Instantiated megafunction \"transfer:inst2\|lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 32 " "Info: Parameter \"LPM_WIDTH\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 43 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../72/quartus/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../72/quartus/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/altshift.tdf" 30 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "transfer:inst2\|lpm_add_sub:Add1\|altshift:result_ext_latency_ffs transfer:inst2\|lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"transfer:inst2\|lpm_add_sub:Add1\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"transfer:inst2\|lpm_add_sub:Add1\"" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 43 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "transfer:inst2\|lpm_add_sub:Add1 " "Info: Instantiated megafunction \"transfer:inst2\|lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 32 " "Info: Parameter \"LPM_WIDTH\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 43 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "transfer:inst2\|lpm_add_sub:Add1\|altshift:carry_ext_latency_ffs transfer:inst2\|lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"transfer:inst2\|lpm_add_sub:Add1\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"transfer:inst2\|lpm_add_sub:Add1\"" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.tdf" 288 2 0 } } { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 43 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "transfer:inst2\|lpm_add_sub:Add1 " "Info: Instantiated megafunction \"transfer:inst2\|lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 32 " "Info: Parameter \"LPM_WIDTH\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 43 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|uart\|transfer:inst2\|state 5 " "Info: State machine \"\|uart\|transfer:inst2\|state\" contains 5 states" {  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 14 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|uart\|reciever:inst1\|state 5 " "Info: State machine \"\|uart\|reciever:inst1\|state\" contains 5 states" {  } { { "reciever.vhd" "" { Text "D:/altera/example/uart/reciever.vhd" 13 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|uart\|transfer:inst2\|state " "Info: Selected Auto state machine encoding method for state machine \"\|uart\|transfer:inst2\|state\"" {  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 14 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|uart\|transfer:inst2\|state " "Info: Encoding result for state machine \"\|uart\|transfer:inst2\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "transfer:inst2\|state.x_stop " "Info: Encoded state bit \"transfer:inst2\|state.x_stop\"" {  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 14 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "transfer:inst2\|state.x_shift " "Info: Encoded state bit \"transfer:inst2\|state.x_shift\"" {  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 14 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "transfer:inst2\|state.x_wait " "Info: Encoded state bit \"transfer:inst2\|state.x_wait\"" {  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 14 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "transfer:inst2\|state.x_start " "Info: Encoded state bit \"transfer:inst2\|state.x_start\"" {  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 14 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "transfer:inst2\|state.x_idle " "Info: Encoded state bit \"transfer:inst2\|state.x_idle\"" {  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 14 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart\|transfer:inst2\|state.x_idle 00000 " "Info: State \"\|uart\|transfer:inst2\|state.x_idle\" uses code string \"00000\"" {  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 14 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart\|transfer:inst2\|state.x_start 00011 " "Info: State \"\|uart\|transfer:inst2\|state.x_start\" uses code string \"00011\"" {  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 14 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart\|transfer:inst2\|state.x_wait 00101 " "Info: State \"\|uart\|transfer:inst2\|state.x_wait\" uses code string \"00101\"" {  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 14 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart\|transfer:inst2\|state.x_shift 01001 " "Info: State \"\|uart\|transfer:inst2\|state.x_shift\" uses code string \"01001\"" {  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 14 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart\|transfer:inst2\|state.x_stop 10001 " "Info: State \"\|uart\|transfer:inst2\|state.x_stop\" uses code string \"10001\"" {  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 14 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 14 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|uart\|reciever:inst1\|state " "Info: Selected Auto state machine encoding method for state machine \"\|uart\|reciever:inst1\|state\"" {  } { { "reciever.vhd" "" { Text "D:/altera/example/uart/reciever.vhd" 13 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|uart\|reciever:inst1\|state " "Info: Encoding result for state machine \"\|uart\|reciever:inst1\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "reciever:inst1\|state.r_stop " "Info: Encoded state bit \"reciever:inst1\|state.r_stop\"" {  } { { "reciever.vhd" "" { Text "D:/altera/example/uart/reciever.vhd" 13 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "reciever:inst1\|state.r_sample " "Info: Encoded state bit \"reciever:inst1\|state.r_sample\"" {  } { { "reciever.vhd" "" { Text "D:/altera/example/uart/reciever.vhd" 13 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "reciever:inst1\|state.r_wait " "Info: Encoded state bit \"reciever:inst1\|state.r_wait\"" {  } { { "reciever.vhd" "" { Text "D:/altera/example/uart/reciever.vhd" 13 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "reciever:inst1\|state.r_center " "Info: Encoded state bit \"reciever:inst1\|state.r_center\"" {  } { { "reciever.vhd" "" { Text "D:/altera/example/uart/reciever.vhd" 13 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "reciever:inst1\|state.r_start " "Info: Encoded state bit \"reciever:inst1\|state.r_start\"" {  } { { "reciever.vhd" "" { Text "D:/altera/example/uart/reciever.vhd" 13 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart\|reciever:inst1\|state.r_start 00000 " "Info: State \"\|uart\|reciever:inst1\|state.r_start\" uses code string \"00000\"" {  } { { "reciever.vhd" "" { Text "D:/altera/example/uart/reciever.vhd" 13 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart\|reciever:inst1\|state.r_center 00011 " "Info: State \"\|uart\|reciever:inst1\|state.r_center\" uses code string \"00011\"" {  } { { "reciever.vhd" "" { Text "D:/altera/example/uart/reciever.vhd" 13 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart\|reciever:inst1\|state.r_wait 00101 " "Info: State \"\|uart\|reciever:inst1\|state.r_wait\" uses code string \"00101\"" {  } { { "reciever.vhd" "" { Text "D:/altera/example/uart/reciever.vhd" 13 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart\|reciever:inst1\|state.r_sample 01001 " "Info: State \"\|uart\|reciever:inst1\|state.r_sample\" uses code string \"01001\"" {  } { { "reciever.vhd" "" { Text "D:/altera/example/uart/reciever.vhd" 13 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart\|reciever:inst1\|state.r_stop 10001 " "Info: State \"\|uart\|reciever:inst1\|state.r_stop\" uses code string \"10001\"" {  } { { "reciever.vhd" "" { Text "D:/altera/example/uart/reciever.vhd" 13 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "reciever.vhd" "" { Text "D:/altera/example/uart/reciever.vhd" 13 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "transfer:inst2\|xcnt16\[4\] data_in GND " "Warning (14130): Reduced register \"transfer:inst2\|xcnt16\[4\]\" with stuck data_in port to stuck value GND" {  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 22 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "transfer.vhd" "" { Text "D:/altera/example/uart/transfer.vhd" 22 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "336 " "Info: Implemented 336 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "313 " "Info: Implemented 313 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Info: Allocated 159 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 04 16:03:08 2009 " "Info: Processing ended: Wed Mar 04 16:03:08 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:29 " "Info: Elapsed time: 00:00:29" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -