delay_unit.v

来自「it is used to find traffic」· Verilog 代码 · 共 34 行

//
// Verilog Module dwt2_lib.delay_unit.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 11:12:20 03/28/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module delay_unit(in,out,clock,reset) ;
  input [23:0] in;
  input clock,reset;
  output [23:0] out;
  reg [23:0] out;
  //reg [23:0] delay;
  
  always@(posedge clock or negedge reset)
  begin
    if(!reset)
    begin
    out<=24'b0;
    //delay<=24'b0;
    end
    else
    begin
   // out<=delay;
    out<=in;
    end
  end
  // ### Please start your Verilog code here ###
endmodule