image_ram_controller.v

it is used to find traffic

//
// Verilog Module dwt_final_lib.image_ram_contrller.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 11:25:55 04/25/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module image_ram_controller(clk,reset,out1,out2,finish);
  input clk,reset;
  output [7:0] out1,out2;
  output finish;
  
   wire [7:0] in1,in2;
   reg [12:0] addr1,addr2;
   
   reg [12:0] count;
   reg finish;
   reg enable1,enable2;
   
   initial
   begin
     $readmemb("D:/even.txt",ram1.mem);
     $readmemb("D:/odd.txt",ram2.mem);
   end
  
  always@(posedge clk or negedge reset)
  begin
    if(!reset)
    begin
    addr1<=13'b0;
    addr2<=13'b0;
    count<=13'b0;
    enable1<=1'b1;
    enable2<=1'b1;
    end
    else 
    begin
      addr1<=addr1+13'b1;
      addr2<=addr2+13'b1;
      count<=count+1'b1;
    end
  end
  
  always@(count)
  begin
    if(count==13'b1111111111111)
    begin
    finish<=1'b1;
    enable1<=1'b0;
    enable2<=1'b0;
    end
    else
    begin
    finish<=1'b0;
    enable1<=1'b1;
    enable2<=1'b1;
    end
  end
     
  image_ram ram1(clk,reset,in1,out1,addr1,1'b0,enable1);
  image_ram ram2(clk,reset,in2,out2,addr2,1'b0,enable2);

endmodule