dwt2.v

it is used to find traffic

//
// Verilog Module dwt_final_lib.dwt2.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 12:17:40 04/15/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module dwt2(in1,in2,clock,reset,out1,out2,enable);
  
  input [7:0] in1,in2;
  input clock,reset,enable;
  output [23:0] out1,out2;
  
  reg [23:0] out1,out2; 
  wire [23:0] inter1,inter2,inter2_del,out_rp1,out_rp2,out_cp1,out_cp2;
  
  always@(posedge clock or negedge reset)
  begin
    if(!reset)
    begin
      out1<=24'b0;
      out2<=24'b0;
    end
    else
    begin
    if(enable==1'b1)
    begin
    out1<=out_cp1;
    out2<=out_cp2;
    end
    else
    begin
    out1<=24'bz;
    out2<=24'bz;
    end
  end
end
  
 int2fixed i2f1(in1,inter1);
 int2fixed i2f2(in2,inter2);   
 delay_unit delu(inter2,inter2_del,clock,reset); 
 row_proc rp(inter1,inter2_del,clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en,out_rp1,out_rp2);
 column_proc cp(out_rp1,out_rp2,clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en,out_cp1,out_cp2);  
 fsm fsm2(clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en);  
  


// ### Please start your Verilog code here ###
endmodule