idwt2.v

it is used to find traffic

//
// Verilog Module dwt_final_lib.idwt2.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 15:47:55 04/25/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module idwt2(in1,in2,clock,reset,out1,out2,enable);
    
    input [23:0] in1,in2;
    input clock,reset,enable;
    output [23:0] out1,out2;
    
    reg [23:0] out1,out2;  
    wire [23:0] out_cp1,out_cp2,out_rp1,out_rp2;   
    
    always@(enable)
    begin
      if(enable==1'b1)
      begin
      out1<=out_cp1;
      out2<=out_cp2;
      end
      else
      begin
      out1<=24'bz;
      out2<=24'bz;
      end
    end
     
   column_proc_idwt cp2(in1,in2,clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en,out_cp1,out_cp2);
   row_proc_idwt rp2(out_cp1,out_cp2,clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en,out_rp1,out_rp2);
   fsm fsm3(clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en);  


// ### Please start your Verilog code here ###
endmodule