demux.v

来自「it is used to find traffic」· Verilog 代码 · 共 31 行

//
// Verilog Module dwt_final_lib.demux.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 15:34:21 05/04/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module demux(in,out1,out2,select);
  input [23:0] in;
  input select;
  output [23:0] out1,out2;
  
  reg [23:0] out1,out2;
  
  always@(in or select)
  begin
    case(select)
    1'b0: out1<=in;
          
    1'b1: out2<=in;
  endcase
  end
    
  
// ### Please start your Verilog code here ###
endmodule