idwt2_tb.v

it is used to find traffic

//
// Verilog Module dwt_final_lib.idwt2_tb.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 16:44:44 04/25/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module idwt2_tb ;

  reg [23:0] in1,in2;
  reg clock,reset;
  wire [23:0] out1,out2;
  
  initial 
  begin
    in1=24'b000000000011000000000000;
    in2=24'b000000000011000000000000;
    clock=1'b1;
    reset=1'b1;
    #2 reset=1'b0;
    #3 reset=1'b1;
  end
  
  always
  #10 clock=!clock;
  
 idwt2 idwt2_1(in1,in2,clock,reset,out1,out2);  
// ### Please start your Verilog code here ###
endmodule