top_module.v

it is used to find traffic

//
// Verilog Module dwt_final_lib.Top_module.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 15:30:32 05/03/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module Top_module(clk,reset,coeff,done);
  
  input clk,reset;
  input [4:0] coeff;
  output done;
  
  reg dwt_done,done;
  reg [15:0] count1,count2,count3;
  
  wire finish;
  reg enable3,enable4,enable5,enable6,enable7,enable8,enable9,enable_dwt,enable_idwt,r_w_en3,r_w_en4,r_w_en6,r_w_en7,r_w_en8,r_w_en9;
  reg [12:0] addr3,addr4,addr5,addr6,addr7,addr8,addr9;
  
  wire [23:0] out_ex_out;
  wire [23:0] out1,out2,out3,out4,odwt_1,odwt_2,out2_inter;
  wire [23:0] out_ex,out_inter1;
  wire [7:0] in1,in2,out6,out7,out8,out9,int_out1,int_out2;
  wire out5;
  
  wire [7:0] in1_inter,in2_inter;
 
  
  integer k,l,i;
  
  
  assign out_ex_out=out_ex + {10'b0,out5&coeff[4],out5&coeff[3],out5&coeff[2],out5&coeff[1],out5&coeff[0],9'b0}; 
  assign in1_inter=in1+{3'b0,coeff};
  assign in2_inter=in2+{3'b0,coeff};
  
  initial
  begin
    $readmemb("D:/watermark.txt",ram5.mem);
    
    k= $fopen("D:/even_out.txt");
    l= $fopen("D:/odd_out.txt");
     #1300000
     for(i=0;i<=8191;i=i+1)
      $fdisplayb(k,ram8.mem[i]);
     for(i=0;i<=8191;i=i+1)
     $fdisplayb(l,ram9.mem[i]);  
   end
   
 always@(posedge clk or negedge reset)
  begin
    if(!reset)
    begin
      enable3<=1'b0;
      enable4<=1'b0;
      enable6<=1'b0;
      enable7<=1'b0;
      
      
      enable8<=1'b1;
      enable9<=1'b1;
      addr8<=13'b1111111111111;
      addr9<=13'b1111111111111;
      r_w_en8<=1'b1;
      r_w_en9<=1'b1;
      
      // enable5<=1'b0;
      enable_dwt<=1'b1;
      enable_idwt<=1'b0;
      count1<=16'b0;
      count3<=16'b0;
      dwt_done<=1'b0;
    end
    else
    begin
      addr8<=addr8+13'b1;
      addr9<=addr9+13'b1;
      
      //if(addr9==13'b1111111111111)
//      begin
//      enable8<=1'b0;
//      enable9<=1'b0;
//      end
      
      count1<=count1+16'b1;   
      count3<=count3+16'b1;   
      addr3<=addr3+13'b1;
      addr4<=addr4+13'b1;
      addr6<=addr6+13'b1;
      addr7<=addr7+13'b1;
      
      if(finish==1'b1)
      count2<=16'b0;
      else
      count2<=count2+16'b1;
      
      //if(dwt_done==1'b1)
//      begin
//      count3<=16'b0;
//      enable_idwt<=1'b1;
//      end
//      else
//      count3<=count3+16'b1;
//     
      if(count1==16'd33)
      begin
      enable3<=1'b1;
      r_w_en3<=1'b1;
      addr3<=13'b1111111111111;      
      end
      if(count1==16'd34)
      begin
      enable4<=1'b1;
      r_w_en4<=1'b1;
      addr4<=13'b1111111111111;      
      end
      
       if(count2==16'd35)
       begin
       enable3<=1'b1;
       r_w_en3<=1'b0;
       addr3<=13'b0;
       done<=1'b1;
       end
       if(count2==16'd36)
       begin
       enable4<=1'b1;
       r_w_en4<=1'b0;
       addr4<=13'b0;
       end
       
       if(dwt_done==1'b1 && count3==16'd34)
       begin
       enable6<=1'b0;
       r_w_en6<=1'b1;
       addr6<=13'b0;
       enable_idwt<=1'b1;              
       end
       
       if(dwt_done==1'b1 && count3==16'd35)
       begin
       enable7<=1'b0;
       r_w_en7<=1'b1;
       addr7<=13'b0;       
       end
       
       if(addr4==12'b111111111111)
       begin
       dwt_done<=1'b1;
       count3<=16'b0;
       end
       
       if(addr7==12'b111111111111)
       done<=1'b1;
       
      
   end
  end
  
  initial
  begin
  $readmemb("E:/dwt_even.txt",ram6.mem);
  $readmemb("E:/dwt_odd.txt",ram7.mem);
  end
   
   always@(posedge clk or negedge reset)
   begin
     
     if(!reset)
     enable5<=1'b0;
     else
     begin 
     if(count1==16'd35)
     begin
     enable5<=1'b1;
     addr5<=12'b0;
     end      
     else if(count1>=16'd35 && count1[0]==1'b1)
     begin
     enable5<=1'b1;
     addr5<=addr5+12'b1;
     end
     else
     enable5<=1'b0;
     end
  end
     
  image_ram_controller  irc(clk,reset,in1,in2,finish);
  dwt2  dwt_proc(in1,in2,clk,reset,out1,out2,enable_dwt);
  dwt2_ram  ram3(clk,reset,out1,out3,addr3,r_w_en3,enable3);
  demux demux1(out2,out_inter1,out_ex,count1[0]);
  mux mux1(out_inter1,out_ex_out,out2_inter,count1[0]);
  dwt2_ram  ram4(clk,reset,out2_inter,out4,addr4,r_w_en4,enable4);
  idwt2 idwt_proc(out3,out4,clk,reset,odwt_1,odwt_2,enable_idwt);
  fixed2int f2i1(odwt_1,int_out1);
  fixed2int f2i2(odwt_2,int_out2);
  final_ram ram6(clk,reset,int_out1,out6,addr6,r_w_en6,enable6);
  final_ram ram7(clk,reset,int_out2,out7,addr7,r_w_en7,enable7);
  watermark_ram ram5(clk,reset,in5,out5,addr5,1'b0,enable5);
  
  final_ram ram8(clk,reset,in1_inter,out8,addr8,r_w_en8,enable8);
  final_ram ram9(clk,reset,in2_inter,out9,addr9,r_w_en9,enable9);

// ### Please start your Verilog code here ###
endmodule