watermark_controller.v

来自「it is used to find traffic」· Verilog 代码 · 共 37 行

//
// Verilog Module dwt_final_lib.watermark_controller.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 14:16:41 04/27/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module watermark_controller(clk,reset,out1,out2);
  input clk,reset;
  output  out1,out2;
   wire  in1,in2;
   wire [11:0] addr1,addr2;
  
  always@(posedge clk or negedge reset)
  begin
    if(!reset)
    begin
    addr1<=12'b0;
    addr2<=12'b0;
    end
    else 
    begin
    addr1<=addr1+12'b1;
    addr2<=addr2+12'b1;
    end
  end
     
  image_ram ram1(clk,reset,in1,out1,addr1,1'b1);
  image_ram ram2(clk,reset,in2,out2,addr2,1'b1);

endmodule