prediction_filter_tb.v

来自「it is used to find traffic」· Verilog 代码 · 共 43 行

//
// Verilog Module dwt2_lib.prediction_filter_tb.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 12:27:50 03/28/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module prediction_filter_tb ;
  reg [23:0] in1,in2;
  reg clock,reset;
  wire [23:0] m_out6,m_out7;
  
  initial 
  begin
    clock=1'b0;
    reset=1'b0;
    in1=24'b000000000010000000000000;
    in2=24'b000000000010000000000000;
    #2 reset=1'b1;
    #3 reset=1'b0;
    #6 reset=1'b1;
    #4 reset=1'b0;
    #3 reset=1'b1;
 end
  
  always
    #5 clock=!clock;
  
//always
//  begin
//    #10 in1=~in1;
//    #15 in2=~in2;
//  end
  
prediction_filter pf1(in1,in2,clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en,m_out6,m_out7);
fsm fsm1(clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en);  
 
endmodule