watermark_embedder.v

来自「it is used to find traffic」· Verilog 代码 · 共 62 行

//
// Verilog Module dwt_final_lib.Watermark_Embedder.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 14:31:23 04/27/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module Watermark_Embedder(Watermark_coeff,Enable,clk,start,reset);
  
  input [1:0] Watermark_coeff;
  input Enable;
  input clk,start,reset;
  
  reg [23:0] watermarked_pixel;
  
  assign enable4=Enable;
  
  always@(posedge clk or negedge start)
  begin
    if(!start)
    begin
    addr<=12'b0;
    addr4<=12'b0;
    r_w_en<=1'b0;
    r_w_en4<=1'b0;
    end
    else
    begin
      if(Enable==1'b1)
      begin
      addr=addr+12'b1;
      addr4<=addr4+12'b1;
      r_w_en4<=1'b1;
      if(out==1'b1)
       case(Watermark_coeff)
        2'b00:watermarked_pixel<=out_HH+24'b0;
        2'b01:watermarked_pixel<=out_HH+24'b000000000000000000011110;
        2'b10:watermarked_pixel<=out_HH+24'b000000000000000111100000;
        2'b11:watermarked_pixel<=out_HH+24'b000000000001111000000000;
      endcase
      else
      watermarked_pixel<=out_HH;
      end
    end
  end
  
  always@(negedge clk )
  begin
   r_w_en4<=1'b0;
   in_HH<=watermarked_pixel; 
  end
 

watermark_ram Wram(clk,reset,in,out,addr,r_w_en);
dwt_ram HH(clk,reset,in_HH,out_HH,addr4,r_w_en4,enable4);
// ### Please start your Verilog code here ###
endmodule