row_proc_idwt.v

it is used to find traffic

//
// Verilog Module dwt_final_lib.row_proc_idwt.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 14:20:24 04/25/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module row_proc_idwt(in1,in2,clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en,out17,out18);
  
  input [23:0] in1,in2;
  input clock,reset;
  input Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en;
  output [23:0] out17,out18;
  
  wire [23:0] out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15,out16,out17,out18;
  wire [23:0] m_out1,m_out2,m_out3,l_out1,l_out2,l_out3;
  wire [23:0] shi_out1,shi_out2,add_out1,add_out2,add_out3,add_out4;
  
  adder add1(m_out1,m_out2,add_out1);
  adder add2(out4,out5,add_out2);
  adder add3(l_out2,m_out3,add_out3);
  adder add4(out15,out16,add_out4);
  
  shifter_2 shi1(out2,shi_out1);
  shifter_4 shi2(out12,shi_out2);
  
  delay_unit del1(in1,out1,clock,reset);
  delay_unit del2(add_out1,out2,clock,reset);
  delay_unit del3(l_out1,out3,clock,reset);
  delay_unit del4(out1,out4,clock,reset);
  delay_unit del5(shi_out1,out5,clock,reset);
  delay_unit del6(out3,out6,clock,reset);
  delay_unit del7(add_out2,out7,clock,reset);
  delay_unit del8(out6,out8,clock,reset);
  delay_unit del9(out7,out9,clock,reset);
  delay_unit del10(out8,out10,clock,reset);
  delay_unit del11(l_out2,out11,clock,reset);
  delay_unit del12(add_out3,out12,clock,reset);
  delay_unit del13(l_out3,out13,clock,reset);
  delay_unit del14(out11,out14,clock,reset);
  delay_unit del15(shi_out2,out15,clock,reset);
  delay_unit del16(out13,out16,clock,reset);
  delay_unit del17(out14,out17,clock,reset);
  delay_unit del18(add_out4,out18,clock,reset);
    
  line_buffer lb1(clock,reset,in1,l_out1);
  line_buffer lb2(clock,reset,out9,l_out2);
  line_buffer lb3(clock,reset,out10,l_out3);
  
  MUX_2 mux1(in2,l_out1,Ext_en1,m_out1);
  MUX_2 mux2(in2,l_out1,Ext_en1,m_out2);
  MUX_2 mux3(out9,l_out3,Ext_en3,m_out3);
  
  
  // ### Please start your Verilog code here ###
  endmodule