column_processor_tb.v

it is used to find traffic

//
// Verilog Module final_year_proj_lib.column_processor_tb.arch_name
//
// Created:
//          by - admin.UNKNOWN (LENOVO-7FE010A7)
//          at - 23:16:16 02/28/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module column_processor_tb ;
  reg [23:0] in1,in2;
  reg clock,reset;
  wire [23:0] out17,out18;
  
  initial 
  begin
    clock=1'b0;
    reset=1'b0;
    in1=24'b000101010100000000000000;
    in2=24'b000001010100000000000000;
    #2 reset=1'b1;
    #3 reset=1'b0;
    #6 reset=1'b1;
    #4 reset=1'b0;
    #3 reset=1'b1;
 end
  
  always
    #5 clock=!clock;
    
  
  always
  begin
    #10 in1=~in1;
    #15 in2=~in2;
  end
  
column_proc cp(in1,in2,clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en,out17,out18);
fsm fsm1(clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en);  
 
endmodule