cla_4.v

it is used to find traffic

//
// Verilog Module dwt2_lib.cla_4.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 10:56:42 02/20/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module cla_4(in1,in2,cin,out_sum,out_carry);
  
  input [3:0] in1,in2;
  input cin;
  //input sum_diff;
  output [3:0] out_sum;
  output out_carry;
  
  wire [3:0] in1,in2,out_sum;
  wire out_carry,cin;
  wire [3:0] g,p;
  wire c1,c2,c3;
  
  
  //assign in1_inter[0] = in1[0]^sum_diff;
  //assign in1_inter[1] = in1[1]^sum_diff; 
  //assign in1_inter[2] = in1[2]^sum_diff;
  //assign in1_inter[3] = in1[3]^sum_diff;
  //assign in1_inter = in1_inter+sum_diff;
  
         
  assign      p = in1^in2;
  assign      g = in1&in2;
        
  assign       c1 = g[0]|(p[0]&cin);
  assign       c2 = g[1]|(p[1]&g[0])|(p[1]&p[0]&cin);
  assign       c3 = g[2]|(p[2]&g[1])|(p[2]&p[1]&g[0])|(p[2]&p[1]&p[0]&cin);
  assign       out_carry = g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0])|(p[3]&p[2]&p[1]&p[0]&cin);
        
        
  assign       out_sum[0] = in1[0]^in2[0]^cin;
  assign       out_sum[1] = in1[1]^in2[1]^c1;
  assign       out_sum[2] = in1[2]^in2[2]^c2;
  assign       out_sum[3] = in1[3]^in2[3]^c3;


// ### Please start your Verilog code here ###
endmodule