column_proc_idwt.v

it is used to find traffic

//
// Verilog Module dwt_final_lib.column_proc_idwt.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 14:20:57 04/25/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module column_proc_idwt (in1,in2,clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en,out1,out2);
  
  input [23:0] in1,in2;
  input clock,reset;
  input  Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en;
  output [23:0] out1,out2;
  
  wire [23:0] out1,out2;
  wire [23:0] in_out1,in_out2;
    
  update_filter uf2(in1,in2,clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en,in_out1,in_out2);
  prediction_filter pf2(in_out1,in_out2,clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en,out1,out2);
  
 // fsm fsm1(clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en);
  
endmodule