mux.v

it is used to find traffic

//
// Verilog Module dwt_final_lib.mux.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 15:34:02 05/04/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module mux(in1,in2,out,select);
  input [23:0] in1,in2;
  input select;
  output [23:0] out;
  
  reg [23:0] out;
  
  always@(in1 or in2 or select)
  begin
    case(select)
    1'b0: out<=in1;
    1'b1: out<=in2;
  endcase
  end
    
  


// ### Please start your Verilog code here ###
endmodule