prediction_filter.v

it is used to find traffic

//
// Verilog Module dwt2_lib.row_processor.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 11:25:18 03/28/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module prediction_filter(in1,in2,clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en,m_out6,m_out7);
  input [23:0] in1,in2;
  input clock,reset;
  input Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en;
  output [23:0] m_out6,m_out7;
  
  //wire [23:0] m_out6,m_out7;
  wire [23:0] out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14;
  wire [23:0] m_out1,m_out2,m_out3,m_out4,m_out5;
  wire [23:0] s_out,a_out1,a_out2;
  
  
  
  delay_unit D1(in1,out1,clock,reset);
  delay_unit D2(out1,out2,clock,reset);
  delay_unit D3(out2,out3,clock,reset);
  delay_unit D4(in2,out4,clock,reset);
  delay_unit D5(out4,out5,clock,reset);
  delay_unit D6(out5,out6,clock,reset);
  delay_unit D7(out6,out7,clock,reset);
  delay_unit D8(out3,out8,clock,reset);
  delay_unit D9(out7,out9,clock,reset);
  delay_unit D10(a_out1,out10,clock,reset);
  delay_unit D11(out8,out11,clock,reset);
  delay_unit D12(out9,out12,clock,reset);
  delay_unit D13(s_out,out13,clock,reset);
  delay_unit D14(a_out2,out14,clock,reset);
  
  MUX_2 M1(out1,out3,Ext_en3,m_out1);
  MUX_2 M2(out5,out7,Ext_en3,m_out2);
  MUX_2 M3(m_out1,m_out2,sel_en,m_out3);
  MUX_2 M4(out3,out7,sel_en,m_out4);
  MUX_2 M5(out8,out9,sel_en,m_out5);
  MUX_2 M6(out11,out14,sel_en,m_out6);
  MUX_2 M7(out14,out12,sel_en,m_out7);
  
  shifter_2 S1(out10,s_out);
  
  adder A1(m_out4,m_out3,a_out1);
  adder A2(m_out5,(~(out13)+1'b1),a_out2);
  
  
  //fsm fsm1(clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en);
  
// ### Please start your Verilog code here ###
endmodule