int2fixed.v

it is used to find traffic

//
// Verilog Module dwt2_lib.int2fixed.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 15:45:20 01/30/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps

module int2fixed(int_in,fixed_out); //input is signed representation
  input [7:0] int_in;
  output [23:0] fixed_out;          //1 bit sign 10 bit integral 13 bit exponent
  reg [23:0] fixed_out;
  
  always@(int_in)
  begin
    fixed_out[23]   <= int_in[7];
    if(int_in[7]==1'b0)
    begin
    fixed_out[22:13]<={3'b0,int_in[6:0]};
    fixed_out[12:0] <=13'b0;
    end
    else
    begin
    fixed_out[22:13]<={3'b111,~(int_in[6:0])+1'b1};
    fixed_out[12:0] <=13'b0;
    end
  end
  
  


// ### Please start your Verilog code here ###
endmodule