fsm.v

it is used to find traffic

//
// Verilog Module dwt2_lib.fsm.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 16:00:47 03/21/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module fsm (clock,reset,Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en);
  input clock,reset;
  output Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en;
  reg Ext_en1,Ext_en2,Ext_en3,Ext_en4,sel_en;
  reg [1:0] state;
  
  always@(posedge clock or negedge reset)
  begin
    if(!reset)
    state<=2'b00;
    else
    begin
      case(state)
      2'b00:
            begin
            Ext_en1<=1'b0;
            Ext_en2<=1'b0;
            Ext_en3<=1'b0;
            Ext_en4<=1'b0;
            sel_en<=1'b0;
            state<=2'b01;            
            end
      2'b01:
            begin
            Ext_en1<=1'b1;
            Ext_en2<=1'b1;
            Ext_en3<=1'b0;
            Ext_en4<=1'b0;
            sel_en<=1'b1;
            state<=2'b10;
            end
      2'b10:
            begin
            Ext_en1<=1'b0;
            Ext_en2<=1'b0;
            Ext_en3<=1'b0;
            Ext_en4<=1'b0;
            sel_en<=1'b0;
            state<=2'b11;
            end                        
      2'b11:
            begin
            Ext_en1<=1'b0;
            Ext_en2<=1'b0;
            Ext_en3<=1'b1;
            Ext_en4<=1'b1;
            sel_en<=1'b1;
            state<=2'b00;
            end
        endcase
      end
 end           

// ### Please start your Verilog code here ###
endmodule