dwt2_tb.v

来自「it is used to find traffic」· Verilog 代码 · 共 36 行

//
// Verilog Module dwt_final_lib.dwt2_tb.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 10:48:14 04/16/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module dwt2_tb ;
  
  reg [7:0] in1,in2;
  reg clock,reset;
  reg enable;
  wire [23:0] out1,out2;
  
  initial 
  begin
    in1=8'b1;
    in2=8'b1;
    enable=1'b1;
    clock=1'b1;
    reset=1'b1;
    #2 reset=1'b0;
    #3 reset=1'b1;
  end
  
  always
  #10 clock=!clock;
  
 dwt2 dwt2_1(in1,in2,clock,reset,out1,out2,enable);  
// ### Please start your Verilog code here ###
endmodule