line_buffer.v

来自「it is used to find traffic」· Verilog 代码 · 共 40 行

//
// Verilog Module dwt2_lib.line_buffer.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 15:45:44 03/28/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module line_buffer(clock,reset,in,out);
  input [23:0] in;
  input clock,reset;
  output [23:0] out;
  reg [23:0] del[7:0];
  reg [23:0] out;
  
 
  always@(posedge clock or negedge reset)
  begin
    if(!reset)
     out<=24'b0;
     else
     begin
     del[0]<=in;
     del[1]<=del[0];
     del[2]<=del[1];
     del[3]<=del[2];
     del[4]<=del[3];
     del[5]<=del[4];
     del[6]<=del[5];
     del[7]<=del[6];
     out<=del[7];
    end
   end
 
// ### Please start your Verilog code here ###
endmodule