dwt2_ram_controller.v

it is used to find traffic

//
// Verilog Module dwt_final_lib.dwt_ram_controller.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 14:45:04 04/26/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module dwt2_ram_controller (clk,reset,in1,in2,out1,out2);
    input clk,reset;
    input [23:0] in1,in2;
    output [23:0] out1,out2;
    
    wire [23:0] in1,in2;
    reg [13:0] addr1,addr2,addr3,addr4;
    reg r_w_en1,r_w_en2,r_w_en3,r_w_en4;
    reg [23:0] in_LL,in_LH,in_HL,in_HH;
    reg enable1,enable2,enable3,enable4;
    reg [2:0] count1;
    reg count2;
    
    
    always@(posedge clk or negedge reset)
    begin
      if(!reset)
      begin
      count1<=3'b0;
      count2<=1'b0;  
      enable1<=1'b0;
      enable2<=1'b0;
      enable3<=1'b0;
      enable4<=1'b0;
      end
      else 
      begin
        if(count1==3'd7)
        begin
        count1<=count1+3'b1;
        count2<=!count2;
        end
        else
        begin
          count1<=count1+3'b1;
        case(count2)
        1'b0:
             begin
             enable1<=1'b1;
             enable3<=1'b1;
             enable2<=1'b0;
             enable4<=1'b0;
             addr1<=addr1+12'b1;
             addr3<=addr3+12'b1;
             in_LL<=in1;
             in_HL<=in2;
             r_w_en1<=1'b1;
             r_w_en3<=1'b1;
             end
        1'b1:
            begin
            enable1<=1'b0;
            enable3<=1'b0;
            enable2<=1'b1;
            enable4<=1'b1;
            addr2<=addr2+12'b1;
            addr4<=addr4+12'b1;
            in_LH<=in1;
            in_HH<=in2;
            r_w_en2<=1'b1;
            r_w_en4<=1'b1;
            end
        endcase
      end
    end
 end
       
    dwt2_ram dwt_ram1(clk,reset,in_1,out_1,addr1,r_w_en1,enable1);
    dwt2_ram dwt_ram2(clk,reset,in_2,out_,addr2,r_w_en2,enable2);
    
//    dwt2_ram HL(clk,reset,in_HL,out_HL,addr3,r_w_en3,enable3);
//    dwt2_ram HH(clk,reset,in_HH,out_HH,addr4,r_w_en4,enable4);
  
  
  // ### Please start your Verilog code here ###
  endmodule