xianshi.rpt

利用FPGA编写的键盘译码程序

_LC061   = LCELL( VCC $  VCC);

-- Node name is '~43819~1' 
-- Equation name is '~43819~1', location is LC013, type is buried.
-- synthesized logic cell 
_LC013   = LCELL( _EQ017 $  GND);
  _EQ017 =  _LC069 & !~27288~1 &  ~42639~1 & !~42657~1
         #  _LC021 & !~42639~1 & !~42657~1;

-- Node name is '~43820~1' 
-- Equation name is '~43820~1', location is LC075, type is buried.
-- synthesized logic cell 
_LC075   = LCELL( _EQ018 $  VCC);
  _EQ018 = !_LC013 & !_LC061 & !~42679~1
         # !_LC078 &  ~42679~1;

-- Node name is '~43828~1' 
-- Equation name is '~43828~1', location is LC001, type is output.
 ~43828~1 = LCELL( _EQ019 $  GND);
  _EQ019 =  _LC007 & !~22971~1 &  ~42699~1 & !~42719~1
         #  _LC075 & !~42699~1 & !~42719~1;

-- Node name is '~43898~1' 
-- Equation name is '~43898~1', location is LC026, type is buried.
-- synthesized logic cell 
_LC026   = LCELL( _EQ020 $  VCC);
  _EQ020 = !_LC050 & !~43900~1;

-- Node name is '~43899~1' 
-- Equation name is '~43899~1', location is LC050, type is buried.
-- synthesized logic cell 
_LC050   = LCELL( VCC $  VCC);

-- Node name is '~43901~1' 
-- Equation name is '~43901~1', location is LC025, type is buried.
-- synthesized logic cell 
_LC025   = LCELL( _EQ021 $  VCC);
  _EQ021 = !_LC002 & !_LC058;

-- Node name is '~43902~1' 
-- Equation name is '~43902~1', location is LC058, type is buried.
-- synthesized logic cell 
_LC058   = LCELL( VCC $  VCC);

-- Node name is '~43903~1' 
-- Equation name is '~43903~1', location is LC002, type is buried.
-- synthesized logic cell 
_LC002   = LCELL( _EQ022 $  GND);
  _EQ022 =  _LC026 & !~42699~1;

-- Node name is '~43904~1' 
-- Equation name is '~43904~1', location is LC018, type is buried.
-- synthesized logic cell 
_LC018   = LCELL( _EQ023 $  VCC);
  _EQ023 = !_LC037 & !_LC051;

-- Node name is '~43905~1' 
-- Equation name is '~43905~1', location is LC051, type is buried.
-- synthesized logic cell 
_LC051   = LCELL( VCC $  VCC);

-- Node name is '~43906~1' 
-- Equation name is '~43906~1', location is LC037, type is buried.
-- synthesized logic cell 
_LC037   = LCELL( _EQ024 $  GND);
  _EQ024 =  _LC025 & !~42719~1;

-- Node name is '~43907~1' 
-- Equation name is '~43907~1', location is LC019, type is buried.
-- synthesized logic cell 
_LC019   = LCELL( _EQ025 $  VCC);
  _EQ025 = !_LC020 & !_LC057;

-- Node name is '~43908~1' 
-- Equation name is '~43908~1', location is LC057, type is buried.
-- synthesized logic cell 
_LC057   = LCELL( VCC $  VCC);

-- Node name is '~43909~1' 
-- Equation name is '~43909~1', location is LC020, type is buried.
-- synthesized logic cell 
_LC020   = LCELL( _EQ026 $  GND);
  _EQ026 =  _LC018 & !~42739~1;

-- Node name is '~43917~1' 
-- Equation name is '~43917~1', location is LC052, type is buried.
-- synthesized logic cell 
_LC052   = LCELL( VCC $  VCC);

-- Node name is '~43918~1' 
-- Equation name is '~43918~1', location is LC092, type is buried.
-- synthesized logic cell 
_LC092   = LCELL( _EQ027 $  GND);
  _EQ027 =  _LC096 &  ~42759~1 & !~42779~1 & !~42797~1
         #  _LC090 & !~17215~1 &  ~42779~1 & !~42797~1
         #  _LC019 & !~42759~1 & !~42779~1 & !~42797~1;

-- Node name is '~43920~1' 
-- Equation name is '~43920~1', location is LC059, type is buried.
-- synthesized logic cell 
_LC059   = LCELL( VCC $  VCC);

-- Node name is '~43922~1' 
-- Equation name is '~43922~1', location is LC056, type is output.
 ~43922~1 = LCELL( _EQ028 $  VCC);
  _EQ028 = !_LC052 & !_LC059 & !_LC092 & !~42839~1
         # !_LC059 &  ~42817~1 & !~42839~1
         # !_LC016 &  ~42839~1;

-- Node name is '~43982~1' 
-- Equation name is '~43982~1', location is LC010, type is buried.
-- synthesized logic cell 
_LC010   = LCELL( _EQ029 $  VCC);
  _EQ029 = !_LC047 & !_LC062;

-- Node name is '~43983~1' 
-- Equation name is '~43983~1', location is LC062, type is buried.
-- synthesized logic cell 
_LC062   = LCELL( VCC $  VCC);

-- Node name is '~43984~1' 
-- Equation name is '~43984~1', location is LC047, type is buried.
-- synthesized logic cell 
_LC047   = LCELL( _EQ030 $  GND);
  _EQ030 = !~42719~1 &  ~43979~1;

-- Node name is '~43985~1' 
-- Equation name is '~43985~1', location is LC012, type is buried.
-- synthesized logic cell 
_LC012   = LCELL( _EQ031 $  VCC);
  _EQ031 = !_LC017 & !_LC033;

-- Node name is '~43986~1' 
-- Equation name is '~43986~1', location is LC033, type is buried.
-- synthesized logic cell 
_LC033   = LCELL( VCC $  VCC);

-- Node name is '~43987~1' 
-- Equation name is '~43987~1', location is LC017, type is buried.
-- synthesized logic cell 
_LC017   = LCELL( _EQ032 $  GND);
  _EQ032 =  _LC010 & !~42739~1;

-- Node name is '~43995~1' 
-- Equation name is '~43995~1', location is LC034, type is buried.
-- synthesized logic cell 
_LC034   = LCELL( VCC $  VCC);

-- Node name is '~43996~1' 
-- Equation name is '~43996~1', location is LC081, type is buried.
-- synthesized logic cell 
_LC081   = LCELL( _EQ033 $  GND);
  _EQ033 =  _LC084 &  ~42759~1 & !~42779~1 & !~42797~1
         #  _LC091 & !~17215~1 &  ~42779~1 & !~42797~1
         #  _LC012 & !~42759~1 & !~42779~1 & !~42797~1;

-- Node name is '~43998~1' 
-- Equation name is '~43998~1', location is LC042, type is buried.
-- synthesized logic cell 
_LC042   = LCELL( VCC $  VCC);

-- Node name is '~44000~1' 
-- Equation name is '~44000~1', location is LC053, type is output.
 ~44000~1 = LCELL( _EQ034 $  VCC);
  _EQ034 = !_LC034 & !_LC042 & !_LC081 & !~42839~1
         # !_LC042 &  ~42817~1 & !~42839~1
         # !_LC005 &  ~42839~1;

-- Node name is '~44042~1' 
-- Equation name is '~44042~1', location is LC008, type is buried.
-- synthesized logic cell 
_LC008   = LCELL( _EQ035 $  VCC);
  _EQ035 = !_LC040 & !~44044~1;

-- Node name is '~44043~1' 
-- Equation name is '~44043~1', location is LC040, type is buried.
-- synthesized logic cell 
_LC040   = LCELL( VCC $  VCC);

-- Node name is '~44045~1' 
-- Equation name is '~44045~1', location is LC006, type is buried.
-- synthesized logic cell 
_LC006   = LCELL( _EQ036 $  VCC);
  _EQ036 = !_LC038 & !_LC039;

-- Node name is '~44046~1' 
-- Equation name is '~44046~1', location is LC039, type is buried.
-- synthesized logic cell 
_LC039   = LCELL( VCC $  VCC);

-- Node name is '~44047~1' 
-- Equation name is '~44047~1', location is LC038, type is buried.
-- synthesized logic cell 
_LC038   = LCELL( _EQ037 $  GND);
  _EQ037 =  _LC008 & !~42619~1;

-- Node name is '~44052~1' 
-- Equation name is '~44052~1', location is LC036, type is buried.
-- synthesized logic cell 
_LC036   = LCELL( VCC $  VCC);

-- Node name is '~44053~1' 
-- Equation name is '~44053~1', location is LC003, type is buried.
-- synthesized logic cell 
_LC003   = LCELL( _EQ038 $  GND);
  _EQ038 =  _LC070 & !~27288~1 &  ~42639~1 & !~42657~1
         #  _LC006 & !~42639~1 & !~42657~1;

-- Node name is '~44054~1' 
-- Equation name is '~44054~1', location is LC073, type is buried.
-- synthesized logic cell 
_LC073   = LCELL( _EQ039 $  VCC);
  _EQ039 = !_LC003 & !_LC036 & !~42679~1
         # !_LC079 &  ~42679~1;

-- Node name is '~44061~1' 
-- Equation name is '~44061~1', location is LC043, type is buried.
-- synthesized logic cell 
_LC043   = LCELL( VCC $  VCC);

-- Node name is '~44062~1' 
-- Equation name is '~44062~1', location is LC015, type is buried.
-- synthesized logic cell 
_LC015   = LCELL( _EQ040 $  GND);
  _EQ040 =  _LC074 & !~22971~1 &  ~42699~1 & !~42719~1
         #  _LC073 & !~42699~1 & !~42719~1;

-- Node name is '~44063~1' 
-- Equation name is '~44063~1', location is LC028, type is buried.
-- synthesized logic cell 
_LC028   = LCELL( _EQ041 $  VCC);
  _EQ041 = !_LC015 & !_LC043 & !~42739~1
         # !_LC093 &  ~42739~1;

-- Node name is '~44073~1' 
-- Equation name is '~44073~1', location is LC046, type is buried.
-- synthesized logic cell 
_LC046   = LCELL( VCC $  VCC);

-- Node name is '~44074~1' 
-- Equation name is '~44074~1', location is LC085, type is buried.
-- synthesized logic cell 
_LC085   = LCELL( _EQ042 $  GND);
  _EQ042 =  _LC086 &  ~42759~1 & !~42779~1 & !~42797~1
         #  _LC094 & !~17215~1 &  ~42779~1 & !~42797~1
         #  _LC028 & !~42759~1 & !~42779~1 & !~42797~1;

-- Node name is '~44076~1' 
-- Equation name is '~44076~1', location is LC041, type is buried.
-- synthesized logic cell 
_LC041   = LCELL( VCC $  VCC);

-- Node name is '~44078~1' 
-- Equation name is '~44078~1', location is LC049, type is output.
 ~44078~1 = LCELL( _EQ043 $  VCC);
  _EQ043 = !_LC041 & !_LC046 & !_LC085 & !~42839~1
         # !_LC041 &  ~42817~1 & !~42839~1
         # !_LC029 &  ~42839~1;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Device-Specific Information:                  d:\vhdl文档\矩阵键盘\xianshi.rpt
xianshi1

***** Logic for device 'xianshi1' compiled without errors.




Device: EPM7096LC68-7

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    MultiVolt I/O                              = OFF



Device-Specific Information:                  d:\vhdl文档\矩阵键盘\xianshi.rpt
xianshi1

** ERROR SUMMARY **

Info: Chip 'xianshi1' in device 'EPM7096LC68-7' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
Info: Chip 'xianshi1' in device 'EPM7096LC68-7' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
              ~  ~  ~     ~  ~                    R  R     R  R  
              4  4  4     4  4                    E  E     E  E  
              3  3  3     3  2  V                 S  S     S  S  
              9  3  4     2  8  C                 E  E  V  E  E  
              3  8  6     2  3  C                 R  R  C  R  R  
              0  5  3  G  9  9  I  G  G  G  G  G  V  V  C  V  V  
              ~  ~  ~  N  ~  ~  N  N  N  N  N  N  E  E  I  E  E  
              1  1  1  D  1  1  T  D  D  D  D  D  D  D  O  D  D  
            -----------------------------------------------------_ 
          /   9  8  7  6  5  4  3  2  1 68 67 66 65 64 63 62 61   | 
~43852~1 | 10                                                  60 | ~43151~1 
   VCCIO | 11                                                  59 | RESERVED 
~43775~1 | 12                                                  58 | GND 
~44008~1 | 13                                                  57 | ~44087~1 
~44000~1 | 14                                                  56 | ~42859~1 
~43208~1 | 15                                                  55 | ~42817~1 
     GND | 16                                                  54 | sel3 
~43922~1 | 17                                                  53 | VCCIO 
~43844~1 | 18                  EPM7096LC68-7                   52 | sel2 
~43696~1 | 19                                                  51 | sel1 
~43540~1 | 20                                                  50 | sel0 
   VCCIO | 21                                                  49 | ~42737~1 
~42897~1 | 22                                                  48 | GND 
~43306~1 | 23                                                  47 | ~20093~1 
~44078~1 | 24                                                  46 | ~15776~1 
~43766~1 | 25                                                  45 | ~42797~1 
     GND | 26                                                  44 | ~42877~1