xianshi.rpt

利用FPGA编写的键盘译码程序

LC96 -> - - - - - - - - - - - - * - - | - - - - - * | <-- ~19281~1
LC84 -> - - - - - - - - - - - - - * - | - - - - - * | <-- ~19329~1
LC86 -> - - - - - - - - - - - - - - * | - - - - - * | <-- ~19377~1

Pin
37   -> - - - - - - - - - - - * * * * | - - - - - * | <-- ~17215~1
20   -> - - - - - - - - - - - * * * * | - - - - - * | <-- ~42759~1
19   -> - - - - - - - - - - - * * * * | - - - - - * | <-- ~42779~1
25   -> - - - - - - - - - - - * * * * | - - - - - * | <-- ~42797~1
18   -> - - - - - - - - - - - * - - - | - - - - - * | <-- ~43751~1
LC19 -> - - - - - - - - - - - - * - - | - - - - - * | <-- ~43907~1
LC12 -> - - - - - - - - - - - - - * - | - - - - - * | <-- ~43985~1
LC28 -> - - - - - - - - - - - - - - * | - - - - - * | <-- ~44063~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                  d:\vhdl文档\矩阵键盘\xianshi.rpt
xianshi

** EQUATIONS **

~17215~1 : INPUT;
~22971~1 : INPUT;
~27288~1 : INPUT;
~42619~1 : INPUT;
~42639~1 : INPUT;
~42657~1 : INPUT;
~42679~1 : INPUT;
~42699~1 : INPUT;
~42719~1 : INPUT;
~42739~1 : INPUT;
~42759~1 : INPUT;
~42779~1 : INPUT;
~42797~1 : INPUT;
~42817~1 : INPUT;
~42839~1 : INPUT;
~43576~1 : INPUT;
~43654~1 : INPUT;
~43751~1 : INPUT;
~43810~1 : INPUT;
~43900~1 : INPUT;
~43979~1 : INPUT;
~44044~1 : INPUT;

-- Node name is '~13431~1' 
-- Equation name is '~13431~1', location is LC082, type is buried.
-- synthesized logic cell 
_LC082   = LCELL( VCC $  VCC);

-- Node name is '~13527~1' 
-- Equation name is '~13527~1', location is LC016, type is buried.
-- synthesized logic cell 
_LC016   = LCELL( VCC $  VCC);

-- Node name is '~13575~1' 
-- Equation name is '~13575~1', location is LC005, type is buried.
-- synthesized logic cell 
_LC005   = LCELL( VCC $  VCC);

-- Node name is '~13623~1' 
-- Equation name is '~13623~1', location is LC029, type is buried.
-- synthesized logic cell 
_LC029   = LCELL( VCC $  VCC);

-- Node name is '~17743~1' 
-- Equation name is '~17743~1', location is LC083, type is buried.
-- synthesized logic cell 
_LC083   = LCELL( VCC $  VCC);

-- Node name is '~17839~1' 
-- Equation name is '~17839~1', location is LC090, type is buried.
-- synthesized logic cell 
_LC090   = LCELL( VCC $  VCC);

-- Node name is '~17887~1' 
-- Equation name is '~17887~1', location is LC091, type is buried.
-- synthesized logic cell 
_LC091   = LCELL( VCC $  VCC);

-- Node name is '~17935~1' 
-- Equation name is '~17935~1', location is LC094, type is buried.
-- synthesized logic cell 
_LC094   = LCELL( VCC $  VCC);

-- Node name is '~19185~1' 
-- Equation name is '~19185~1', location is LC095, type is buried.
-- synthesized logic cell 
_LC095   = LCELL( VCC $  VCC);

-- Node name is '~19281~1' 
-- Equation name is '~19281~1', location is LC096, type is buried.
-- synthesized logic cell 
_LC096   = LCELL( VCC $  VCC);

-- Node name is '~19329~1' 
-- Equation name is '~19329~1', location is LC084, type is buried.
-- synthesized logic cell 
_LC084   = LCELL( VCC $  VCC);

-- Node name is '~19377~1' 
-- Equation name is '~19377~1', location is LC086, type is buried.
-- synthesized logic cell 
_LC086   = LCELL( VCC $  VCC);

-- Node name is '~20818~1' 
-- Equation name is '~20818~1', location is LC093, type is buried.
-- synthesized logic cell 
_LC093   = LCELL( VCC $  VCC);

-- Node name is '~23403~1' 
-- Equation name is '~23403~1', location is LC089, type is buried.
-- synthesized logic cell 
_LC089   = LCELL( VCC $  VCC);

-- Node name is '~23547~1' 
-- Equation name is '~23547~1', location is LC007, type is buried.
-- synthesized logic cell 
_LC007   = LCELL( VCC $  VCC);

-- Node name is '~23691~1' 
-- Equation name is '~23691~1', location is LC074, type is buried.
-- synthesized logic cell 
_LC074   = LCELL( VCC $  VCC);

-- Node name is '~24847~1' 
-- Equation name is '~24847~1', location is LC076, type is buried.
-- synthesized logic cell 
_LC076   = LCELL( VCC $  VCC);

-- Node name is '~24895~1' 
-- Equation name is '~24895~1', location is LC077, type is buried.
-- synthesized logic cell 
_LC077   = LCELL( VCC $  VCC);

-- Node name is '~24991~1' 
-- Equation name is '~24991~1', location is LC078, type is buried.
-- synthesized logic cell 
_LC078   = LCELL( VCC $  VCC);

-- Node name is '~25135~1' 
-- Equation name is '~25135~1', location is LC079, type is buried.
-- synthesized logic cell 
_LC079   = LCELL( VCC $  VCC);

-- Node name is '~27768~1' 
-- Equation name is '~27768~1', location is LC065, type is buried.
-- synthesized logic cell 
_LC065   = LCELL( VCC $  VCC);

-- Node name is '~27864~1' 
-- Equation name is '~27864~1', location is LC069, type is buried.
-- synthesized logic cell 
_LC069   = LCELL( VCC $  VCC);

-- Node name is '~28008~1' 
-- Equation name is '~28008~1', location is LC070, type is buried.
-- synthesized logic cell 
_LC070   = LCELL( VCC $  VCC);

-- Node name is '~43574~1' 
-- Equation name is '~43574~1', location is LC027, type is buried.
-- synthesized logic cell 
_LC027   = LCELL( _EQ001 $  VCC);
  _EQ001 = !_LC066 & !~43576~1;

-- Node name is '~43575~1' 
-- Equation name is '~43575~1', location is LC066, type is buried.
-- synthesized logic cell 
_LC066   = LCELL( VCC $  VCC);

-- Node name is '~43577~1' 
-- Equation name is '~43577~1', location is LC022, type is buried.
-- synthesized logic cell 
_LC022   = LCELL( _EQ002 $  VCC);
  _EQ002 = !_LC048 & !_LC072;

-- Node name is '~43578~1' 
-- Equation name is '~43578~1', location is LC072, type is buried.
-- synthesized logic cell 
_LC072   = LCELL( VCC $  VCC);

-- Node name is '~43579~1' 
-- Equation name is '~43579~1', location is LC048, type is buried.
-- synthesized logic cell 
_LC048   = LCELL( _EQ003 $  GND);
  _EQ003 =  _LC027 & !~42619~1;

-- Node name is '~43581~1' 
-- Equation name is '~43581~1', location is LC068, type is buried.
-- synthesized logic cell 
_LC068   = LCELL( VCC $  VCC);

-- Node name is '~43582~1' 
-- Equation name is '~43582~1', location is LC011, type is buried.
-- synthesized logic cell 
_LC011   = LCELL( _EQ004 $  GND);
  _EQ004 =  _LC022 & !~42639~1;

-- Node name is '~43584~1' 
-- Equation name is '~43584~1', location is LC071, type is buried.
-- synthesized logic cell 
_LC071   = LCELL( VCC $  VCC);

-- Node name is '~43586~1' 
-- Equation name is '~43586~1', location is LC080, type is buried.
-- synthesized logic cell 
_LC080   = LCELL( _EQ005 $  VCC);
  _EQ005 = !_LC011 & !_LC068 & !_LC071 & !~42679~1
         # !_LC071 &  ~42657~1 & !~42679~1
         # !_LC076 &  ~42679~1;

-- Node name is '~43594~1' 
-- Equation name is '~43594~1', location is LC004, type is output.
 ~43594~1 = LCELL( _EQ006 $  GND);
  _EQ006 =  _LC089 & !~22971~1 &  ~42699~1 & !~42719~1
         #  _LC080 & !~42699~1 & !~42719~1;

-- Node name is '~43652~1' 
-- Equation name is '~43652~1', location is LC032, type is buried.
-- synthesized logic cell 
_LC032   = LCELL( _EQ007 $  VCC);
  _EQ007 = !_LC035 & !~43654~1;

-- Node name is '~43653~1' 
-- Equation name is '~43653~1', location is LC035, type is buried.
-- synthesized logic cell 
_LC035   = LCELL( VCC $  VCC);

-- Node name is '~43655~1' 
-- Equation name is '~43655~1', location is LC031, type is buried.
-- synthesized logic cell 
_LC031   = LCELL( _EQ008 $  VCC);
  _EQ008 = !_LC024 & !_LC044;

-- Node name is '~43656~1' 
-- Equation name is '~43656~1', location is LC024, type is buried.
-- synthesized logic cell 
_LC024   = LCELL( VCC $  VCC);

-- Node name is '~43657~1' 
-- Equation name is '~43657~1', location is LC044, type is buried.
-- synthesized logic cell 
_LC044   = LCELL( _EQ009 $  GND);
  _EQ009 =  _LC032 & !~42619~1;

-- Node name is '~43662~1' 
-- Equation name is '~43662~1', location is LC009, type is buried.
-- synthesized logic cell 
_LC009   = LCELL( VCC $  VCC);

-- Node name is '~43663~1' 
-- Equation name is '~43663~1', location is LC014, type is buried.
-- synthesized logic cell 
_LC014   = LCELL( _EQ010 $  GND);
  _EQ010 =  _LC065 & !~27288~1 &  ~42639~1 & !~42657~1
         #  _LC031 & !~42639~1 & !~42657~1;

-- Node name is '~43664~1' 
-- Equation name is '~43664~1', location is LC067, type is output.
 ~43664~1 = LCELL( _EQ011 $  VCC);
  _EQ011 = !_LC009 & !_LC014 & !~42679~1
         # !_LC077 &  ~42679~1;

-- Node name is '~43761~1' 
-- Equation name is '~43761~1', location is LC063, type is buried.
-- synthesized logic cell 
_LC063   = LCELL( VCC $  VCC);

-- Node name is '~43762~1' 
-- Equation name is '~43762~1', location is LC087, type is buried.
-- synthesized logic cell 
_LC087   = LCELL( _EQ012 $  GND);
  _EQ012 =  _LC095 &  ~42759~1 & !~42779~1 & !~42797~1
         #  _LC083 & !~17215~1 &  ~42779~1 & !~42797~1
         # !~42759~1 & !~42779~1 & !~42797~1 &  ~43751~1;

-- Node name is '~43764~1' 
-- Equation name is '~43764~1', location is LC055, type is buried.
-- synthesized logic cell 
_LC055   = LCELL( VCC $  VCC);

-- Node name is '~43766~1' 
-- Equation name is '~43766~1', location is LC064, type is output.
 ~43766~1 = LCELL( _EQ013 $  VCC);
  _EQ013 = !_LC055 & !_LC063 & !_LC087 & !~42839~1
         # !_LC055 &  ~42817~1 & !~42839~1
         # !_LC082 &  ~42839~1;

-- Node name is '~43808~1' 
-- Equation name is '~43808~1', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL( _EQ014 $  VCC);
  _EQ014 = !_LC054 & !~43810~1;

-- Node name is '~43809~1' 
-- Equation name is '~43809~1', location is LC054, type is buried.
-- synthesized logic cell 
_LC054   = LCELL( VCC $  VCC);

-- Node name is '~43811~1' 
-- Equation name is '~43811~1', location is LC021, type is buried.
-- synthesized logic cell 
_LC021   = LCELL( _EQ015 $  VCC);
  _EQ015 = !_LC045 & !_LC060;

-- Node name is '~43812~1' 
-- Equation name is '~43812~1', location is LC060, type is buried.
-- synthesized logic cell 
_LC060   = LCELL( VCC $  VCC);

-- Node name is '~43813~1' 
-- Equation name is '~43813~1', location is LC045, type is buried.
-- synthesized logic cell 
_LC045   = LCELL( _EQ016 $  GND);
  _EQ016 =  _LC023 & !~42619~1;

-- Node name is '~43818~1' 
-- Equation name is '~43818~1', location is LC061, type is buried.
-- synthesized logic cell