addbcd.vhd

来自「利用FPGA编写的键盘译码程序」· VHDL 代码 · 共 44 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity addBCD is
   port (   clk: in std_logic;
          start: in std_logic;
          num1 : in std_logic_vector (3 downto 0);
          num2 : in std_logic_vector (3 downto 0);
          outnum : out std_logic_vector (7 downto 0)
        );
end addBCD;

architecture rt1 of addBCD is
 signal q1,q2:integer range 0 to 9;
 signal q3:integer range 0 to 18;
 signal q:integer range 0 to 24;
begin
q1<=conv_integer(num1);
q2<=conv_integer(num2);
process(clk,start,q1,q2)
  begin
    if clk'event and clk='1'then
       if start='1' then
          q3<=q1+q2;
       end if;
    end if;
end process;
process(clk,q3)
  begin
    if clk'event and clk='1'then
       if q3>=10 then
           q<=q3+6;
       else
           q<=q3;
       end if;
    end if;
outnum<=conv_std_logic_vector(q,8);
end process;
end rt1;