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Project Information d:\vhdl文档\矩阵键盘\jia.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 06/24/2008 23:30:56
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
JIA
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
jia EPM7032LC44-6 6 8 0 8 0 25 %
User Pins: 6 8 0
Project Information d:\vhdl文档\矩阵键盘\jia.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Device-Specific Information: d:\vhdl文档\矩阵键盘\jia.rpt
jia
***** Logic for device 'jia' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
o o
i i u u
n n V G G G c G t t
t t C N N N l N 2 2
2 3 a C D D D k D 3 2
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
int1 | 7 39 | out21
int0 | 8 38 | out20
RESERVED | 9 37 | out13
GND | 10 36 | out11
RESERVED | 11 35 | VCC
RESERVED | 12 EPM7032LC44-6 34 | out12
RESERVED | 13 33 | out10
RESERVED | 14 32 | RESERVED
VCC | 15 31 | RESERVED
RESERVED | 16 30 | GND
RESERVED | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R R R R
E E E E N C E E E E E
S S S S D C S S S S S
E E E E E E E E E
R R R R R R R R R
V V V V V V V V V
E E E E E E E E E
D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\vhdl文档\矩阵键盘\jia.rpt
jia
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 5/16( 31%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 8/16( 50%) 8/16( 50%) 0/16( 0%) 13/36( 36%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 13/32 ( 40%)
Total logic cells used: 8/32 ( 25%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 8/32 ( 25%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 4.00
Total fan-in: 32
Total input pins required: 6
Total output pins required: 8
Total bidirectional pins required: 0
Total logic cells required: 8
Total flipflops required: 8
Total product terms required: 16
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: d:\vhdl文档\矩阵键盘\jia.rpt
jia
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 8 0 a
43 - - INPUT G 0 0 0 0 0 0 0 clk
8 (5) (A) INPUT 0 0 0 0 0 2 0 int0
7 (4) (A) INPUT 0 0 0 0 0 2 0 int1
6 (3) (A) INPUT 0 0 0 0 0 2 0 int2
5 (2) (A) INPUT 0 0 0 0 0 2 0 int3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\vhdl文档\矩阵键盘\jia.rpt
jia
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
33 24 B FF + t 0 0 0 2 1 1 0 out10 (:18)
36 22 B FF + t 0 0 0 2 1 1 0 out11 (:17)
34 23 B FF + t 0 0 0 2 1 1 0 out12 (:16)
37 21 B FF + t 0 0 0 2 1 1 0 out13 (:15)
38 20 B FF + t 0 0 0 2 1 1 0 out20 (:22)
39 19 B FF + t 0 0 0 2 1 1 0 out21 (:21)
40 18 B FF + t 0 0 0 2 1 1 0 out22 (:20)
41 17 B FF + t 0 0 0 2 1 1 0 out23 (:19)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl文档\矩阵键盘\jia.rpt
jia
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------- LC24 out10
| +------------- LC22 out11
| | +----------- LC23 out12
| | | +--------- LC21 out13
| | | | +------- LC20 out20
| | | | | +----- LC19 out21
| | | | | | +--- LC18 out22
| | | | | | | +- LC17 out23
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'B'
LC | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC24 -> * - - - - - - - | - * | <-- out10
LC22 -> - * - - - - - - | - * | <-- out11
LC23 -> - - * - - - - - | - * | <-- out12
LC21 -> - - - * - - - - | - * | <-- out13
LC20 -> - - - - * - - - | - * | <-- out20
LC19 -> - - - - - * - - | - * | <-- out21
LC18 -> - - - - - - * - | - * | <-- out22
LC17 -> - - - - - - - * | - * | <-- out23
Pin
4 -> * * * * * * * * | - * | <-- a
43 -> - - - - - - - - | - - | <-- clk
8 -> * - - - * - - - | - * | <-- int0
7 -> - * - - - * - - | - * | <-- int1
6 -> - - * - - - * - | - * | <-- int2
5 -> - - - * - - - * | - * | <-- int3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl文档\矩阵键盘\jia.rpt
jia
** EQUATIONS **
a : INPUT;
clk : INPUT;
int0 : INPUT;
int1 : INPUT;
int2 : INPUT;
int3 : INPUT;
-- Node name is 'out10' = 's10'
-- Equation name is 'out10', location is LC024, type is output.
out10 = DFFE( _EQ001 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = a & out10
# !a & int0;
-- Node name is 'out11' = 's11'
-- Equation name is 'out11', location is LC022, type is output.
out11 = DFFE( _EQ002 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = a & out11
# !a & int1;
-- Node name is 'out12' = 's12'
-- Equation name is 'out12', location is LC023, type is output.
out12 = DFFE( _EQ003 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = a & out12
# !a & int2;
-- Node name is 'out13' = 's13'
-- Equation name is 'out13', location is LC021, type is output.
out13 = DFFE( _EQ004 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = a & out13
# !a & int3;
-- Node name is 'out20' = 's20'
-- Equation name is 'out20', location is LC020, type is output.
out20 = DFFE( _EQ005 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = a & int0
# !a & out20;
-- Node name is 'out21' = 's21'
-- Equation name is 'out21', location is LC019, type is output.
out21 = DFFE( _EQ006 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = a & int1
# !a & out21;
-- Node name is 'out22' = 's22'
-- Equation name is 'out22', location is LC018, type is output.
out22 = DFFE( _EQ007 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = a & int2
# !a & out22;
-- Node name is 'out23' = 's23'
-- Equation name is 'out23', location is LC017, type is output.
out23 = DFFE( _EQ008 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = a & int3
# !a & out23;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\vhdl文档\矩阵键盘\jia.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,150K
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