cnt.vhd

来自「利用FPGA编写的键盘译码程序」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt is
	port( clk:in std_logic;
		  sel2,sel1,sel0:out std_logic);
end cnt;
architecture cnt_arch of cnt is
begin
process(clk)
variable cn:std_logic_vector(2 downto 0);
begin
	if clk'event and clk='1' then
		if cn="111" then
			cn:="000";
		else
			cn:=cn+1;
		end if;
	end if;
sel0<=cn(0);
sel1<=cn(1);
sel2<=cn(2);
end process;
end cnt_arch;