dclk.vhd

来自「利用FPGA编写的键盘译码程序」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dclk is 
	port(clk:in std_logic;
		 divclk:out std_logic);
end dclk;

architecture dclk_arch of dclk is 
begin
process(clk)
variable cnt:std_logic_vector(1 downto 0);
variable a:std_logic;
begin
	if clk'event and clk='1' then
       if(cnt="11") then
           cnt:="00";
           a:=not a;
       else
           cnt:=cnt+1;
       end if;
	end if;
divclk<=a;
end process;
end dclk_arch;