gyima.rpt

利用FPGA编写的键盘译码程序

Pin
22   -> - * - - - - - - - - - - - - * - | * - * * * * | <-- ~PIN001
39   -> - - * * * * * * * * * * * * * - | * * * * * * | <-- ~PIN002
10   -> - - * - * * * * * * * * * * * - | * * * * * * | <-- ~PIN003
9    -> - - * * * * * * * * * * * * * - | * * * * * * | <-- ~PIN004
8    -> - - * * * * * * * * * * * * * - | * * * * * * | <-- ~PIN005
13   -> - - - - - - - - - - - - - - * - | * * * * * * | <-- ~PIN006
32   -> - - - - - - - - - - - - - - * - | * * * * * * | <-- ~PIN007
4    -> - - - - - - - - - - - - - - * - | * * * * * * | <-- ~PIN008
1    -> - - - - - - - - - - - - - - * - | * * * * * * | <-- ~PIN009
7    -> - - - - - - - - - - - - - - * - | * * * * * * | <-- ~PIN010
15   -> - * - * - - - - - - - - - - * - | - - * - * - | <-- ~PIN011
18   -> * - - - - - - - - - - - - - - - | - - - - * * | <-- ~PIN013
28   -> * - - - - - - - - - - - - - - * | - - - - * - | <-- ~PIN019
LC49 -> - * - - - - - - - - - - - - * - | - - - * * - | <-- |XIANSHI:20|~7286~1
LC31 -> * - - - - - - - - - - - - - - - | - - - - * - | <-- |XIANSHI:20|~10265~1
LC50 -> - - - - - - - - - - - - - - * - | - - - - * - | <-- |XIANSHI:20|~43129~2
LC19 -> - * - - - - - - - - - - - - * - | - - - * * - | <-- |XIANSHI:20|~43151~1
LC95 -> - - - - - - - - - - - - - - - * | - - - - * - | <-- |XIANSHI:20|~43223~1
LC37 -> * - - - - - - - - - - - - - - - | - - - - * - | <-- |XIANSHI:20|~43299~1
LC28 -> * - - - - - - - - - - - - - - - | - - - - * - | <-- |XIANSHI:20|~43300~1
LC86 -> * - - - - - - - - - - - - - - - | - - - - * - | <-- |XIANSHI:20|~43302~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                    d:\vhdl文档\矩阵键盘\gyima.rpt
gyima

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

                                       Logic cells placed in LAB 'F'
        +----------------------------- LC84 Q15
        | +--------------------------- LC94 |XIANSHI:20|~42900~1
        | | +------------------------- LC91 |XIANSHI:20|~42900~2
        | | | +----------------------- LC88 |XIANSHI:20|~42981~1
        | | | | +--------------------- LC87 |XIANSHI:20|~42982~2
        | | | | | +------------------- LC85 |XIANSHI:20|~42984~1
        | | | | | | +----------------- LC96 |XIANSHI:20|~43056~1
        | | | | | | | +--------------- LC93 |XIANSHI:20|~43068~1
        | | | | | | | | +------------- LC90 |XIANSHI:20|~43069~1
        | | | | | | | | | +----------- LC89 |XIANSHI:20|~43071~1
        | | | | | | | | | | +--------- LC81 |XIANSHI:20|~43128~1
        | | | | | | | | | | | +------- LC82 |XIANSHI:20|~43145~1
        | | | | | | | | | | | | +----- LC83 |XIANSHI:20|~43206~1
        | | | | | | | | | | | | | +--- LC95 |XIANSHI:20|~43223~1
        | | | | | | | | | | | | | | +- LC86 |XIANSHI:20|~43302~1
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'F'
LC      | | | | | | | | | | | | | | | | A B C D E F |     Logic cells that feed LAB 'F':
LC94 -> * * - - - - - - - - - - - - - | - - - - - * | <-- |XIANSHI:20|~42900~1
LC91 -> - * - - - - - - - - - - - - - | - - - - - * | <-- |XIANSHI:20|~42900~2

Pin
22   -> * - - - * - - - - - - - - - - | * - * * * * | <-- ~PIN001
39   -> - * - * - * * * - * * - * - * | * * * * * * | <-- ~PIN002
10   -> - * * * * * * * - * * - * - * | * * * * * * | <-- ~PIN003
9    -> - * * * * * * * - * * - * - * | * * * * * * | <-- ~PIN004
8    -> - * * * * * * * - * * - * - * | * * * * * * | <-- ~PIN005
13   -> - * * * * * * * - * * - * - - | * * * * * * | <-- ~PIN006
32   -> - * * * * * * * - * * - * - - | * * * * * * | <-- ~PIN007
4    -> - * * * * * * * - * * - * - - | * * * * * * | <-- ~PIN008
1    -> - * * * * * * * - * * - * - - | * * * * * * | <-- ~PIN009
7    -> - * * * * * * * - * * - * - - | * * * * * * | <-- ~PIN010
17   -> - - - - - - - - * - - - - - - | - - * - - * | <-- ~PIN012
18   -> - - - - - - - - * - - * - * * | - - - - * * | <-- ~PIN013
LC58 -> * * * - - - - - - - - - - - - | - - - - - * | <-- |XIANSHI:20|~7145~1
LC77 -> - * - - - - - - - - - - - - - | - - - - - * | <-- |XIANSHI:20|~8572~1
LC74 -> - * - - - - - - - - - - - - - | - - - - - * | <-- |XIANSHI:20|~10025~1
LC69 -> - * - - - - - - - - - - - - - | - - - - - * | <-- |XIANSHI:20|~11464~1
LC76 -> - - - - - - - - - - - * - - - | - - - - - * | <-- |XIANSHI:20|~11608~1
LC70 -> - - - - - - - - - - - - - * - | - - - - - * | <-- |XIANSHI:20|~11656~1
LC71 -> - * - - - - - - - - - - - - - | - - - - - * | <-- |XIANSHI:20|~12901~1
LC54 -> - - - - - - - - * - - - - - - | - - - - - * | <-- |XIANSHI:20|~12994~1
LC32 -> - * * - - - - - - - - - - - - | - - - - - * | <-- |XIANSHI:20|~42821~1
LC26 -> - - - - - - - - * - - * - * - | * - * - - * | <-- |XIANSHI:20|~42837~1
LC11 -> - - - - - - - - * - - - - - - | - - - - - * | <-- |XIANSHI:20|~43061~1
LC34 -> - - - - - - - - - - - * - - - | - - - - - * | <-- |XIANSHI:20|~43140~1
LC3  -> - - - - - - - - - - - * - - - | - - - - - * | <-- |XIANSHI:20|~43141~1
LC36 -> - - - - - - - - - - - * - - - | - - - - - * | <-- |XIANSHI:20|~43143~1
LC35 -> - - - - - - - - - - - - - * - | - - - - - * | <-- |XIANSHI:20|~43218~1
LC6  -> - - - - - - - - - - - - - * - | - - - - - * | <-- |XIANSHI:20|~43219~1
LC44 -> - - - - - - - - - - - - - * - | - - - - - * | <-- |XIANSHI:20|~43221~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                    d:\vhdl文档\矩阵键盘\gyima.rpt
gyima

** EQUATIONS **

~PIN001  : INPUT;
~PIN002  : INPUT;
~PIN003  : INPUT;
~PIN004  : INPUT;
~PIN005  : INPUT;
~PIN006  : INPUT;
~PIN007  : INPUT;
~PIN008  : INPUT;
~PIN009  : INPUT;
~PIN010  : INPUT;
~PIN011  : INPUT;
~PIN012  : INPUT;
~PIN013  : INPUT;
~PIN014  : INPUT;
~PIN015  : INPUT;
~PIN016  : INPUT;
~PIN017  : INPUT;
~PIN018  : INPUT;
~PIN019  : INPUT;
~PIN020  : INPUT;
~PIN021  : INPUT;

-- Node name is 'Q10' 
-- Equation name is 'Q10', location is LC033, type is output.
 Q10     = LCELL( _EQ001 $  GND);
  _EQ001 =  _LC075 & !~PIN001 &  ~PIN018
         #  _LC052 &  ~PIN001 & !~PIN011
         # !~PIN001 & !~PIN018 &  ~PIN024;

-- Node name is 'Q11' 
-- Equation name is 'Q11', location is LC043, type is output.
 Q11     = LCELL( _EQ002 $  GND);
  _EQ002 =  _LC053 &  ~PIN001 & !~PIN011
         #  _LC027 & !~PIN001;

-- Node name is 'Q12' 
-- Equation name is 'Q12', location is LC067, type is output.
 Q12     = LCELL( _EQ003 $  GND);
  _EQ003 =  _LC049 &  ~PIN001 & !~PIN011
         #  _LC019 & !~PIN001;

-- Node name is 'Q13' 
-- Equation name is 'Q13', location is LC056, type is output.
 Q13     = LCELL( _EQ004 $  GND);
  _EQ004 =  _LC079 &  ~PIN001
         #  _LC041 & !~PIN001;

-- Node name is 'Q14' 
-- Equation name is 'Q14', location is LC040, type is output.
 Q14     = LCELL( _EQ005 $  GND);
  _EQ005 =  _LC068 &  ~PIN001 & !~PIN011
         #  _LC018 & !~PIN001;

-- Node name is 'Q15' 
-- Equation name is 'Q15', location is LC084, type is output.
 Q15     = LCELL( _EQ006 $  GND);
  _EQ006 =  _LC058 &  ~PIN001
         #  _LC094 & !~PIN001;

-- Node name is '|XIANSHI:20|~7145~1' 
-- Equation name is '_LC058', type is buried 
-- synthesized logic cell 
_LC058   = LCELL( _EQ007 $  ~PIN002);
  _EQ007 =  ~PIN002 &  ~PIN003 &  ~PIN004 &  ~PIN005
         #  ~PIN002 & !~PIN003 & !~PIN004;

-- Node name is '|XIANSHI:20|~7190~1' 
-- Equation name is '_LC068', type is buried 
-- synthesized logic cell 
_LC068   = LCELL( _EQ008 $  ~PIN002);
  _EQ008 =  ~PIN002 &  ~PIN003 &  ~PIN004 &  ~PIN005
         #  ~PIN002 & !~PIN003 & !~PIN004;

-- Node name is '|XIANSHI:20|~7241~1' 
-- Equation name is '_LC079', type is buried 
-- synthesized logic cell 
_LC079   = LCELL( _EQ009 $  GND);
  _EQ009 =  ~PIN002 &  ~PIN004 & !~PIN005 & !~PIN011;

-- Node name is '|XIANSHI:20|~7286~1' 
-- Equation name is '_LC049', type is buried 
-- synthesized logic cell 
_LC049   = LCELL( _EQ010 $  GND);
  _EQ010 =  ~PIN002 &  ~PIN004 & !~PIN005;

-- Node name is '|XIANSHI:20|~7334~1' 
-- Equation name is '_LC053', type is buried 
-- synthesized logic cell 
_LC053   = LCELL( _EQ011 $  GND);
  _EQ011 =  ~PIN002 &  ~PIN004 & !~PIN005;

-- Node name is '|XIANSHI:20|~7382~1' 
-- Equation name is '_LC052', type is buried 
-- synthesized logic cell 
_LC052   = LCELL( _EQ012 $  GND);
  _EQ012 =  ~PIN002 &  ~PIN004 & !~PIN005;

-- Node name is '|XIANSHI:20|~8572~1' 
-- Equation name is '_LC077', type is buried 
-- synthesized logic cell 
_LC077   = LCELL( _EQ013 $  GND);
  _EQ013 =  ~PIN002 &  ~PIN003 &  ~PIN004 & !~PIN005
         #  ~PIN002 &  ~PIN003 & !~PIN004 &  ~PIN005;

-- Node name is '|XIANSHI:20|~8682~1' 
-- Equation name is '_LC078', type is buried 
-- synthesized logic cell 
_LC078   = LCELL( _EQ014 $  GND);
  _EQ014 =  ~PIN002 &  ~PIN003 &  ~PIN004 & !~PIN005
         #  ~PIN002 &  ~PIN003 & !~PIN004 &  ~PIN005;

-- Node name is '|XIANSHI:20|~8824~1' 
-- Equation name is '_LC075', type is buried 
-- synthesized logic cell 
_LC075   = LCELL( _EQ015 $  GND);
  _EQ015 =  ~PIN002 &  ~PIN003 &  ~PIN004 & !~PIN005
         #  ~PIN002 &  ~PIN003 & !~PIN004 &  ~PIN005;

-- Node name is '|XIANSHI:20|~10025~1' 
-- Equation name is '_LC074', type is buried 
-- synthesized logic cell 
_LC074   = LCELL( _EQ016 $  ~PIN002);
  _EQ016 =  ~PIN002 &  ~PIN003 &  ~PIN004 &  ~PIN005
         #  ~PIN002 & !~PIN003 & !~PIN004;

-- Node name is '|XIANSHI:20|~10164~1' 
-- Equation name is '_LC073', type is buried 
-- synthesized logic cell 
_LC073   = LCELL( _EQ017 $  ~PIN002);
  _EQ017 =  ~PIN002 &  ~PIN003 &  ~PIN004 &  ~PIN005
         #  ~PIN002 & !~PIN003 & !~PIN004;

-- Node name is '|XIANSHI:20|~10265~1' 
-- Equation name is '_LC031', type is buried 
-- synthesized logic cell 
_LC031   = LCELL( _EQ018 $  GND);
  _EQ018 =  ~PIN002 & !~PIN003 &  ~PIN004 & !~PIN014;

-- Node name is '|XIANSHI:20|~11464~1' 
-- Equation name is '_LC069', type is buried 
-- synthesized logic cell 
_LC069   = LCELL( _EQ019 $  ~PIN002);
  _EQ019 =  ~PIN002 &  ~PIN003 &  ~PIN004 &  ~PIN005
         #  ~PIN002 & !~PIN003 & !~PIN004;

-- Node name is '|XIANSHI:20|~11608~1' 
-- Equation name is '_LC076', type is buried 
-- synthesized logic cell 
_LC076   = LCELL( _EQ020 $  ~PIN002);
  _EQ020 =  ~PIN002 &  ~PIN003 &  ~PIN004 &  ~PIN005
         #  ~PIN002 & !~PIN003 & !~PIN004;

-- Node name is '|XIANSHI:20|~11656~1' 
-- Equation name is '_LC070', type is buried 
-- synthesized logic cell 
_LC070   = LCELL( _EQ021 $  ~PIN002);
  _EQ021 =  ~PIN002 &  ~PIN003 &  ~PIN004 &  ~PIN005
         #  ~PIN002 & !~PIN003 & !~PIN004;

-- Node name is '|XIANSHI:20|~12901~1' 
-- Equation name is '_LC071', type is buried 
-- synthesized logic cell 
_LC071   = LCELL( _EQ022 $  GND);
  _EQ022 =  ~PIN002 &  ~PIN003 & !~PIN004 &  ~PIN005
         #  ~PIN002 & !~PIN003 &  ~PIN004
         #  ~PIN002 &  ~PIN004 & !~PIN005;

-- Node name is '|XIANSHI:20|~12951~1' 
-- Equation name is '_LC072', type is buried 
-- synthesized logic cell