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Logic cells placed in LAB 'A'
+----------------- LC1 |XIANSHI:20|~42817~1
| +--------------- LC10 |XIANSHI:20|~42982~1
| | +------------- LC7 |XIANSHI:20|~42986~1
| | | +----------- LC2 |XIANSHI:20|~42991~1
| | | | +--------- LC12 |XIANSHI:20|~43059~1
| | | | | +------- LC11 |XIANSHI:20|~43061~1
| | | | | | +----- LC3 |XIANSHI:20|~43141~1
| | | | | | | +--- LC6 |XIANSHI:20|~43219~1
| | | | | | | | +- LC9 |XIANSHI:20|~43231~1
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'A':
LC1 -> - - * - - * * * - | * - * - - - | <-- |XIANSHI:20|~42817~1
LC10 -> - - * - - - - - - | * - - - - - | <-- |XIANSHI:20|~42982~1
LC7 -> - - - * - - - - - | * - - - - - | <-- |XIANSHI:20|~42986~1
LC12 -> - - - - - * - - - | * - - - - - | <-- |XIANSHI:20|~43059~1
Pin
22 -> - * - - - - - - - | * - * * * * | <-- ~PIN001
39 -> - * - - * - - - - | * * * * * * | <-- ~PIN002
10 -> - * - - * - - - - | * * * * * * | <-- ~PIN003
9 -> - * - - * - - - - | * * * * * * | <-- ~PIN004
8 -> - * - - - - - - - | * * * * * * | <-- ~PIN005
13 -> * * - * - - - - - | * * * * * * | <-- ~PIN006
32 -> * * - * - - - - - | * * * * * * | <-- ~PIN007
4 -> * * - * - - - - - | * * * * * * | <-- ~PIN008
1 -> * * - * - - - - - | * * * * * * | <-- ~PIN009
7 -> * * - * - - - - - | * * * * * * | <-- ~PIN010
14 -> - - - - - - * * - | * - - - - - | <-- ~PIN015
20 -> - - - - - - - - * | * - * - - - | <-- ~PIN018
LC17 -> - - - - * * * * - | * - - - - - | <-- ~PIN022
LC72 -> - - * - - - - - - | * - - - - - | <-- |XIANSHI:20|~12951~1
LC57 -> - - - - - * - - - | * - - - - - | <-- |XIANSHI:20|~14438~1
LC59 -> - - - - - - * - - | * - - - - - | <-- |XIANSHI:20|~15920~1
LC55 -> - - - - - - - * - | * - - - - - | <-- |XIANSHI:20|~15968~1
LC26 -> - - * - - - - - - | * - * - - * | <-- |XIANSHI:20|~42837~1
LC88 -> - - * - - - - - - | * - - - - - | <-- |XIANSHI:20|~42981~1
LC87 -> - * - - - - - - - | * - - - - - | <-- |XIANSHI:20|~42982~2
LC85 -> - - * - - - - - - | * - - - - - | <-- |XIANSHI:20|~42984~1
LC18 -> - * - - - - - - - | * - * - - - | <-- |XIANSHI:20|~42995~1
LC96 -> - - - - - * - - - | * - - - - - | <-- |XIANSHI:20|~43056~1
LC64 -> - - - - - * - - - | * - - - - - | <-- |XIANSHI:20|~43057~1
LC22 -> - - - - - - * - - | * - - - - - | <-- |XIANSHI:20|~43133~1
LC29 -> - - - - - - - * - | * - - - - - | <-- |XIANSHI:20|~43211~1
LC24 -> - - - - - - - - * | * - - - - - | <-- |XIANSHI:20|~43226~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl文档\矩阵键盘\gyima.rpt
gyima
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC17 ~PIN022
| +----------------------------- LC31 |XIANSHI:20|~10265~1
| | +--------------------------- LC32 |XIANSHI:20|~42821~1
| | | +------------------------- LC26 |XIANSHI:20|~42837~1
| | | | +----------------------- LC30 |XIANSHI:20|~42877~1
| | | | | +--------------------- LC21 |XIANSHI:20|~42897~1
| | | | | | +------------------- LC18 |XIANSHI:20|~42995~1
| | | | | | | +----------------- LC20 |XIANSHI:20|~43131~1
| | | | | | | | +--------------- LC22 |XIANSHI:20|~43133~1
| | | | | | | | | +------------- LC19 |XIANSHI:20|~43151~1
| | | | | | | | | | +----------- LC23 |XIANSHI:20|~43209~1
| | | | | | | | | | | +--------- LC29 |XIANSHI:20|~43211~1
| | | | | | | | | | | | +------- LC24 |XIANSHI:20|~43226~1
| | | | | | | | | | | | | +----- LC27 |XIANSHI:20|~43229~1
| | | | | | | | | | | | | | +--- LC25 |XIANSHI:20|~43295~1
| | | | | | | | | | | | | | | +- LC28 |XIANSHI:20|~43300~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'B':
LC20 -> - - - - - - - - * - - - - - - - | - * - - - - | <-- |XIANSHI:20|~43131~1
LC23 -> - - - - - - - - - - - * - - - - | - * - - - - | <-- |XIANSHI:20|~43209~1
LC25 -> - - - - - - - - - - - - - - - * | - * - - - - | <-- |XIANSHI:20|~43295~1
Pin
39 -> - * * - - - * * - - * - - - - - | * * * * * * | <-- ~PIN002
10 -> - * * - - - * * - - * - - - - - | * * * * * * | <-- ~PIN003
9 -> - * * - - - * * - - * - - - - - | * * * * * * | <-- ~PIN004
8 -> - - * - - - * * - - * - - - - - | * * * * * * | <-- ~PIN005
13 -> * - * * * * * - - - - - - - - - | * * * * * * | <-- ~PIN006
32 -> * - * * * * * - - - - - - - - - | * * * * * * | <-- ~PIN007
4 -> * - * * * * * - - - - - - - - - | * * * * * * | <-- ~PIN008
1 -> * - * * * * * - - - - - - - - - | * * * * * * | <-- ~PIN009
7 -> * - * * * * * - - - - - - - - - | * * * * * * | <-- ~PIN010
19 -> - * - - - - - - - - - - - - - - | - * * - - - | <-- ~PIN014
36 -> - - - - - - - - * - - * - - - - | - * - - - - | <-- ~PIN016
30 -> - - - - - - - * * - * * - - - - | - * - - - - | <-- ~PIN017
25 -> - - - - - - - - - - - - - - - * | - * - - - - | <-- ~PIN020
24 -> - - - - - - - - - - - - - - * - | - * - - - - | <-- ~PIN021
LC62 -> - - - - - - - - * - - - - - - - | - * - - - - | <-- |XIANSHI:20|~17364~1
LC60 -> - - - - - - - - - - - * - - - - | - * - - - - | <-- |XIANSHI:20|~17412~1
LC2 -> - - - - - - * - - - - - - - - - | - * - - - - | <-- |XIANSHI:20|~42991~1
LC81 -> - - - - - - - - * - - - - - - - | - * - - - - | <-- |XIANSHI:20|~43128~1
LC65 -> - - - - - - - - * - - - - - - - | - * - - - - | <-- |XIANSHI:20|~43129~1
LC45 -> - - - - - - - - - * - - - - - - | - * - - - - | <-- |XIANSHI:20|~43152~1
LC47 -> - - - - - - - - - * - - - - - - | - * - - - - | <-- |XIANSHI:20|~43153~1
LC83 -> - - - - - - - - - - - * - - - - | - * - - - - | <-- |XIANSHI:20|~43206~1
LC48 -> - - - - - - - - - - - * - - - - | - * - - - - | <-- |XIANSHI:20|~43207~1
LC38 -> - - - - - - - - - - - - * - - - | - * - - - - | <-- |XIANSHI:20|~43227~1
LC66 -> - - - - - - - - - - - - * - - - | - * - - - - | <-- |XIANSHI:20|~43228~1
LC39 -> - - - - - - - - - - - - - * - - | - * - - - - | <-- |XIANSHI:20|~43230~1
LC9 -> - - - - - - - - - - - - - * - - | - * - - - - | <-- |XIANSHI:20|~43231~1
LC42 -> - - - - - - - - - - - - - - * - | - * - - - - | <-- |XIANSHI:20|~43296~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl文档\矩阵键盘\gyima.rpt
gyima
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------------- LC33 Q10
| +--------------------------- LC43 Q11
| | +------------------------- LC40 Q14
| | | +----------------------- LC41 |XIANSHI:20|~43073~1
| | | | +--------------------- LC34 |XIANSHI:20|~43140~1
| | | | | +------------------- LC36 |XIANSHI:20|~43143~1
| | | | | | +----------------- LC45 |XIANSHI:20|~43152~1
| | | | | | | +--------------- LC47 |XIANSHI:20|~43153~1
| | | | | | | | +------------- LC48 |XIANSHI:20|~43207~1
| | | | | | | | | +----------- LC35 |XIANSHI:20|~43218~1
| | | | | | | | | | +--------- LC44 |XIANSHI:20|~43221~1
| | | | | | | | | | | +------- LC38 |XIANSHI:20|~43227~1
| | | | | | | | | | | | +----- LC39 |XIANSHI:20|~43230~1
| | | | | | | | | | | | | +--- LC42 |XIANSHI:20|~43296~1
| | | | | | | | | | | | | | +- LC37 |XIANSHI:20|~43299~1
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'C':
Pin
22 -> * * * - - - - - * - - - - - - | * - * * * * | <-- ~PIN001
39 -> - - - - * * * - * * * * * * * | * * * * * * | <-- ~PIN002
10 -> - - - - * * * - * * * * * * * | * * * * * * | <-- ~PIN003
9 -> - - - - * * * - * * * * * * * | * * * * * * | <-- ~PIN004
8 -> - - - - * * * - * * * * * * * | * * * * * * | <-- ~PIN005
13 -> - - - - - - - - * - - - - - - | * * * * * * | <-- ~PIN006
32 -> - - - - - - - - * - - - - - - | * * * * * * | <-- ~PIN007
4 -> - - - - - - - - * - - - - - - | * * * * * * | <-- ~PIN008
1 -> - - - - - - - - * - - - - - - | * * * * * * | <-- ~PIN009
7 -> - - - - - - - - * - - - - - - | * * * * * * | <-- ~PIN010
15 -> * * * - - - - - * - - - - - - | - - * - * - | <-- ~PIN011
17 -> - - - - - * - - - - * - - - * | - - * - - * | <-- ~PIN012
19 -> - - - - - - - * - - - * - - - | - * * - - - | <-- ~PIN014
20 -> * - - - - - - - - - - - - - - | * - * - - - | <-- ~PIN018
LC80 -> * - - - - - - - - - - - - - - | - - * - - - | <-- ~PIN024
LC68 -> - - * - - - - - - - - - - - - | - - * - - - | <-- |XIANSHI:20|~7190~1
LC53 -> - * - - - - - - - - - - - - - | - - * - - - | <-- |XIANSHI:20|~7334~1
LC52 -> * - - - - - - - - - - - - - - | - - * - - - | <-- |XIANSHI:20|~7382~1
LC78 -> - - - * - - - - - - - - - - - | - - * - - - | <-- |XIANSHI:20|~8682~1
LC75 -> * - - - - - - - - - - - - - - | - - * - - - | <-- |XIANSHI:20|~8824~1
LC73 -> - - - - - - - * - - - - - - - | - - * - - - | <-- |XIANSHI:20|~10164~1
LC1 -> - - - - * - - - - * - - - * - | * - * - - - | <-- |XIANSHI:20|~42817~1
LC26 -> - - - - - * - - - - * - - - * | * - * - - * | <-- |XIANSHI:20|~42837~1
LC30 -> - - - * - - - * - - - * - - - | - - * - - - | <-- |XIANSHI:20|~42877~1
LC21 -> - - - * - - * * - - - - * - - | - - * - - - | <-- |XIANSHI:20|~42897~1
LC18 -> - - * - - - - - - - - - - - - | * - * - - - | <-- |XIANSHI:20|~42995~1
LC93 -> - - - * - - - - - - - - - - - | - - * - - - | <-- |XIANSHI:20|~43068~1
LC90 -> - - - * - - - - - - - - - - - | - - * - - - | <-- |XIANSHI:20|~43069~1
LC89 -> - - - * - - - - - - - - - - - | - - * - - - | <-- |XIANSHI:20|~43071~1
LC82 -> - - - - - - - * - - - - - - - | - - * - - - | <-- |XIANSHI:20|~43145~1
LC51 -> - - - - - - - - * - - - - - - | - - * - - - | <-- |XIANSHI:20|~43207~2
LC27 -> - * - - - - - - * - - - - - - | - - * * - - | <-- |XIANSHI:20|~43229~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl文档\矩阵键盘\gyima.rpt
gyima
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC56 Q13
| +----------------------------- LC58 |XIANSHI:20|~7145~1
| | +--------------------------- LC49 |XIANSHI:20|~7286~1
| | | +------------------------- LC53 |XIANSHI:20|~7334~1
| | | | +----------------------- LC52 |XIANSHI:20|~7382~1
| | | | | +--------------------- LC54 |XIANSHI:20|~12994~1
| | | | | | +------------------- LC57 |XIANSHI:20|~14438~1
| | | | | | | +----------------- LC59 |XIANSHI:20|~15920~1
| | | | | | | | +--------------- LC55 |XIANSHI:20|~15968~1
| | | | | | | | | +------------- LC62 |XIANSHI:20|~17364~1
| | | | | | | | | | +----------- LC60 |XIANSHI:20|~17412~1
| | | | | | | | | | | +--------- LC64 |XIANSHI:20|~43057~1
| | | | | | | | | | | | +------- LC63 |XIANSHI:20|~43057~2
| | | | | | | | | | | | | +----- LC61 |XIANSHI:20|~43057~3
| | | | | | | | | | | | | | +--- LC50 |XIANSHI:20|~43129~2
| | | | | | | | | | | | | | | +- LC51 |XIANSHI:20|~43207~2
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'D':
LC49 -> - - - - - - - - - - - - - - * - | - - - * * - | <-- |XIANSHI:20|~7286~1
LC63 -> - - - - - - - - - - - * - - - - | - - - * - - | <-- |XIANSHI:20|~43057~2
LC61 -> - - - - - - - - - - - * - - - - | - - - * - - | <-- |XIANSHI:20|~43057~3
Pin
22 -> * - - - - - - - - - - * * * * * | * - * * * * | <-- ~PIN001
39 -> - * * * * * * * * * * * - - - - | * * * * * * | <-- ~PIN002
10 -> - * - - - * * * * * * * * * * - | * * * * * * | <-- ~PIN003
9 -> - * * * * * * * * * * * * * * * | * * * * * * | <-- ~PIN004
8 -> - * * * * * - * * * * * * * * * | * * * * * * | <-- ~PIN005
13 -> - - - - - - - - - - - * * * - - | * * * * * * | <-- ~PIN006
32 -> - - - - - - - - - - - * * * * * | * * * * * * | <-- ~PIN007
4 -> - - - - - - - - - - - * * * * * | * * * * * * | <-- ~PIN008
1 -> - - - - - - - - - - - * * * * * | * * * * * * | <-- ~PIN009
7 -> - - - - - - - - - - - * * * - - | * * * * * * | <-- ~PIN010
LC79 -> * - - - - - - - - - - * * * - - | - - - * - - | <-- |XIANSHI:20|~7241~1
LC41 -> * - - - - - - - - - - * - * - - | - - - * - - | <-- |XIANSHI:20|~43073~1
LC19 -> - - - - - - - - - - - - - - * - | - - - * * - | <-- |XIANSHI:20|~43151~1
LC27 -> - - - - - - - - - - - - - - - * | - - * * - - | <-- |XIANSHI:20|~43229~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl文档\矩阵键盘\gyima.rpt
gyima
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+------------------------------- LC80 ~PIN024
| +----------------------------- LC67 Q12
| | +--------------------------- LC68 |XIANSHI:20|~7190~1
| | | +------------------------- LC79 |XIANSHI:20|~7241~1
| | | | +----------------------- LC77 |XIANSHI:20|~8572~1
| | | | | +--------------------- LC78 |XIANSHI:20|~8682~1
| | | | | | +------------------- LC75 |XIANSHI:20|~8824~1
| | | | | | | +----------------- LC74 |XIANSHI:20|~10025~1
| | | | | | | | +--------------- LC73 |XIANSHI:20|~10164~1
| | | | | | | | | +------------- LC69 |XIANSHI:20|~11464~1
| | | | | | | | | | +----------- LC76 |XIANSHI:20|~11608~1
| | | | | | | | | | | +--------- LC70 |XIANSHI:20|~11656~1
| | | | | | | | | | | | +------- LC71 |XIANSHI:20|~12901~1
| | | | | | | | | | | | | +----- LC72 |XIANSHI:20|~12951~1
| | | | | | | | | | | | | | +--- LC65 |XIANSHI:20|~43129~1
| | | | | | | | | | | | | | | +- LC66 |XIANSHI:20|~43228~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'E'
LC | | | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'E':
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