📄 gyima.rpt
字号:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
Device-Specific Information: d:\vhdl文档\矩阵键盘\gyima.rpt
gyima
** ERROR SUMMARY **
Info: Chip 'gyima' in device 'EPM7096LC68-7' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
R R R R R
~ ~ ~ E ~ ~ E E E E
P P P S P V P S S S S
I I I E I C I E E V E E
N N N R N C N R R C R R
0 0 0 G V 0 I G 0 G G G V V C V V
0 0 1 N E 0 N N 0 N N N E E I E E
4 5 0 D D 8 T D 9 D D D D D O D D
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
~PIN003 | 10 60 | RESERVED
VCCIO | 11 59 | RESERVED
RESERVED | 12 58 | GND
~PIN006 | 13 57 | Q15
~PIN015 | 14 56 | RESERVED
~PIN011 | 15 55 | ~PIN024
GND | 16 54 | RESERVED
~PIN012 | 17 53 | VCCIO
~PIN013 | 18 EPM7096LC68-7 52 | RESERVED
~PIN014 | 19 51 | RESERVED
~PIN018 | 20 50 | RESERVED
VCCIO | 21 49 | RESERVED
~PIN001 | 22 48 | GND
~PIN022 | 23 47 | Q12
~PIN021 | 24 46 | RESERVED
~PIN020 | 25 45 | RESERVED
GND | 26 44 | RESERVED
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
Q ~ Q ~ V ~ Q G V ~ R G ~ Q R R V
1 P 1 P C P 1 N C P E N P 1 E E C
1 I 4 I C I 0 D C I S D I 3 S S C
N N I N I N E N E E I
0 0 O 0 N 0 R 0 R R O
1 1 0 T 1 V 0 V V
9 7 7 6 E 2 E E
D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\vhdl文档\矩阵键盘\gyima.rpt
gyima
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 9/16( 56%) 6/ 8( 75%) 16/16(100%) 31/36( 86%)
B: LC17 - LC32 16/16(100%) 8/ 8(100%) 11/16( 68%) 31/36( 86%)
C: LC33 - LC48 15/16( 93%) 8/ 8(100%) 16/16(100%) 32/36( 88%)
D: LC49 - LC64 16/16(100%) 3/ 8( 37%) 16/16(100%) 17/36( 47%)
E: LC65 - LC80 16/16(100%) 2/ 8( 25%) 16/16(100%) 21/36( 58%)
F: LC81 - LC96 15/16( 93%) 1/ 8( 12%) 16/16(100%) 31/36( 86%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 28/48 ( 58%)
Total logic cells used: 87/96 ( 90%)
Total shareable expanders used: 79/96 ( 82%)
Total Turbo logic cells used: 87/96 ( 90%)
Total shareable expanders not available (n/a): 12/96 ( 12%)
Average fan-in: 5.75
Total fan-in: 501
Total input pins required: 21
Total output pins required: 8
Total bidirectional pins required: 0
Total logic cells required: 87
Total flipflops required: 0
Total product terms required: 302
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 63
Synthesized logic cells: 81/ 96 ( 84%)
Device-Specific Information: d:\vhdl文档\矩阵键盘\gyima.rpt
gyima
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
22 (19) (B) INPUT s 0 0 0 0 0 6 9 ~PIN001
39 (53) (D) INPUT s 0 0 0 0 0 0 50 ~PIN002
10 (6) (A) INPUT s 0 0 0 0 0 0 51 ~PIN003
9 (8) (A) INPUT s 0 0 0 0 0 0 56 ~PIN004
8 (9) (A) INPUT s 0 0 0 0 0 0 53 ~PIN005
13 (1) (A) INPUT s 0 0 0 0 0 1 23 ~PIN006
32 (35) (C) INPUT s 0 0 0 0 0 1 25 ~PIN007
4 (16) (A) INPUT s 0 0 0 0 0 1 25 ~PIN008
1 - - INPUT s 0 0 0 0 0 1 25 ~PIN009
7 (12) (A) INPUT s 0 0 0 0 0 1 23 ~PIN010
15 (29) (B) INPUT s 0 0 0 0 0 4 3 ~PIN011
17 (27) (B) INPUT s 0 0 0 0 0 0 4 ~PIN012
18 (25) (B) INPUT s 0 0 0 0 0 1 4 ~PIN013
19 (24) (B) INPUT s 0 0 0 0 0 0 3 ~PIN014
14 (32) (B) INPUT s 0 0 0 0 0 0 2 ~PIN015
36 (49) (D) INPUT s 0 0 0 0 0 0 2 ~PIN016
30 (37) (C) INPUT s 0 0 0 0 0 0 4 ~PIN017
20 (21) (B) INPUT s 0 0 0 0 0 1 1 ~PIN018
28 (41) (C) INPUT s 0 0 0 0 0 1 1 ~PIN019
25 (45) (C) INPUT s 0 0 0 0 0 0 1 ~PIN020
24 (48) (C) INPUT s 0 0 0 0 0 0 1 ~PIN021
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl文档\矩阵键盘\gyima.rpt
gyima
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
23 17 B OUTPUT s t 0 0 0 5 0 0 4 ~PIN022
55 80 E OUTPUT s t 0 0 0 2 4 1 0 ~PIN024
33 33 C OUTPUT t 0 0 0 3 3 0 0 Q10
27 43 C OUTPUT t 0 0 0 2 2 0 0 Q11
47 67 E OUTPUT t 0 0 0 2 2 0 0 Q12
40 56 D OUTPUT t 0 0 0 1 2 0 0 Q13
29 40 C OUTPUT t 0 0 0 2 2 0 0 Q14
57 84 F OUTPUT t 0 0 0 1 2 0 0 Q15
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl文档\矩阵键盘\gyima.rpt
gyima
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 58 D SOFT s t 0 0 0 4 0 1 2 |XIANSHI:20|~7145~1
- 68 E SOFT s t 0 0 0 4 0 1 0 |XIANSHI:20|~7190~1
- 79 E SOFT s t 0 0 0 4 0 1 3 |XIANSHI:20|~7241~1
(36) 49 D SOFT s t 0 0 0 3 0 1 2 |XIANSHI:20|~7286~1
(39) 53 D SOFT s t 0 0 0 3 0 1 0 |XIANSHI:20|~7334~1
- 52 D SOFT s t 0 0 0 3 0 1 0 |XIANSHI:20|~7382~1
(54) 77 E SOFT s t 0 0 0 4 0 0 1 |XIANSHI:20|~8572~1
- 78 E SOFT s t 0 0 0 4 0 0 1 |XIANSHI:20|~8682~1
(52) 75 E SOFT s t 0 0 0 4 0 1 0 |XIANSHI:20|~8824~1
- 74 E SOFT s t 0 0 0 4 0 0 1 |XIANSHI:20|~10025~1
(51) 73 E SOFT s t 0 0 0 4 0 0 1 |XIANSHI:20|~10164~1
- 31 B SOFT s t 0 0 0 4 0 1 0 |XIANSHI:20|~10265~1
(49) 69 E SOFT s t 0 0 0 4 0 0 1 |XIANSHI:20|~11464~1
- 76 E SOFT s t 0 0 0 4 0 0 1 |XIANSHI:20|~11608~1
- 70 E SOFT s t 0 0 0 4 0 0 1 |XIANSHI:20|~11656~1
- 71 E SOFT s t 0 0 0 4 0 0 1 |XIANSHI:20|~12901~1
(50) 72 E SOFT s t 0 0 0 4 0 0 1 |XIANSHI:20|~12951~1
- 54 D SOFT s t 0 0 0 4 0 0 1 |XIANSHI:20|~12994~1
(41) 57 D SOFT s t 0 0 0 3 0 0 1 |XIANSHI:20|~14438~1
(42) 59 D SOFT s t 0 0 0 4 0 0 1 |XIANSHI:20|~15920~1
- 55 D SOFT s t 0 0 0 4 0 0 1 |XIANSHI:20|~15968~1
- 62 D SOFT s t 0 0 0 4 0 0 1 |XIANSHI:20|~17364~1
- 60 D SOFT s t 0 0 0 4 0 0 1 |XIANSHI:20|~17412~1
(13) 1 A SOFT s t 0 0 0 5 0 0 7 |XIANSHI:20|~42817~1
(14) 32 B SOFT s t 0 0 0 9 0 0 2 |XIANSHI:20|~42821~1
- 26 B SOFT s t 0 0 0 5 0 0 7 |XIANSHI:20|~42837~1
- 30 B SOFT s t 0 0 0 5 0 0 3 |XIANSHI:20|~42877~1
(20) 21 B SOFT s t 0 0 0 5 0 0 4 |XIANSHI:20|~42897~1
(64) 94 F SOFT s t 14 0 1 9 8 1 1 |XIANSHI:20|~42900~1
- 91 F SOFT s t 1 0 1 8 2 0 1 |XIANSHI:20|~42900~2
(60) 88 F SOFT s t 0 0 0 9 0 0 1 |XIANSHI:20|~42981~1
- 10 A SOFT s t 16 6 1 10 2 0 1 |XIANSHI:20|~42982~1
- 87 F SOFT s t 1 0 1 9 0 0 1 |XIANSHI:20|~42982~2
- 85 F SOFT s t 0 0 0 9 0 0 1 |XIANSHI:20|~42984~1
- 7 A SOFT s t 0 0 0 0 6 0 1 |XIANSHI:20|~42986~1
- 2 A SOFT s t 0 0 0 5 1 0 1 |XIANSHI:20|~42991~1
- 18 B SOFT s t 11 0 1 9 1 1 1 |XIANSHI:20|~42995~1
(65) 96 F SOFT s t 0 0 0 9 0 0 1 |XIANSHI:20|~43056~1
(45) 64 D SOFT s t 12 4 1 10 4 0 1 |XIANSHI:20|~43057~1
- 63 D SOFT s t 1 0 1 9 1 0 1 |XIANSHI:20|~43057~2
(44) 61 D SOFT s t 1 0 1 9 2 0 1 |XIANSHI:20|~43057~3
(7) 12 A SOFT s t 0 0 0 3 1 0 1 |XIANSHI:20|~43059~1
- 11 A SOFT s t 0 0 0 0 6 0 1 |XIANSHI:20|~43061~1
- 93 F SOFT s t 0 0 0 9 0 0 1 |XIANSHI:20|~43068~1
- 90 F SOFT s t 0 0 0 2 3 0 1 |XIANSHI:20|~43069~1
(61) 89 F SOFT s t 0 0 0 9 0 0 1 |XIANSHI:20|~43071~1
(28) 41 C SOFT s t 0 0 0 0 6 1 2 |XIANSHI:20|~43073~1
(56) 81 F SOFT s t 0 0 0 9 0 0 1 |XIANSHI:20|~43128~1
(46) 65 E SOFT s t 16 8 1 11 3 0 1 |XIANSHI:20|~43129~1
- 50 D SOFT s t 1 0 1 7 2 0 1 |XIANSHI:20|~43129~2
- 20 B SOFT s t 0 0 0 5 0 0 1 |XIANSHI:20|~43131~1
- 22 B SOFT s t 0 0 0 2 4 0 1 |XIANSHI:20|~43133~1
- 34 C SOFT s t 0 0 0 4 1 0 1 |XIANSHI:20|~43140~1
- 3 A SOFT s t 0 0 0 1 4 0 1 |XIANSHI:20|~43141~1
- 36 C SOFT s t 0 0 0 5 1 0 1 |XIANSHI:20|~43143~1
- 82 F SOFT s t 0 0 0 1 5 0 1 |XIANSHI:20|~43145~1
(22) 19 B SOFT s t 0 0 0 0 2 1 2 |XIANSHI:20|~43151~1
(25) 45 C SOFT s t 0 0 0 4 1 0 1 |XIANSHI:20|~43152~1
- 47 C SOFT s t 0 0 0 1 4 0 1 |XIANSHI:20|~43153~1
- 83 F SOFT s t 0 0 0 9 0 0 1 |XIANSHI:20|~43206~1
(24) 48 C SOFT s t 16 10 1 11 2 0 1 |XIANSHI:20|~43207~1
(37) 51 D SOFT s t 1 0 1 6 1 0 1 |XIANSHI:20|~43207~2
- 23 B SOFT s t 0 0 0 5 0 0 1 |XIANSHI:20|~43209~1
(15) 29 B SOFT s t 0 0 0 2 4 0 1 |XIANSHI:20|~43211~1
(32) 35 C SOFT s t 0 0 0 4 1 0 1 |XIANSHI:20|~43218~1
(10) 6 A SOFT s t 0 0 0 1 4 0 1 |XIANSHI:20|~43219~1
- 44 C SOFT s t 0 0 0 5 1 0 1 |XIANSHI:20|~43221~1
- 95 F SOFT s t 0 0 0 1 5 0 1 |XIANSHI:20|~43223~1
(19) 24 B SOFT s t 0 0 0 0 2 0 1 |XIANSHI:20|~43226~1
- 38 C SOFT s t 0 0 0 5 1 0 1 |XIANSHI:20|~43227~1
- 66 E SOFT s t 0 0 0 1 1 0 1 |XIANSHI:20|~43228~1
(17) 27 B SOFT s t 0 0 0 0 2 1 2 |XIANSHI:20|~43229~1
- 39 C SOFT s t 0 0 0 4 1 0 1 |XIANSHI:20|~43230~1
(8) 9 A SOFT s t 0 0 0 1 1 0 1 |XIANSHI:20|~43231~1
(18) 25 B SOFT s t 0 0 0 1 1 0 1 |XIANSHI:20|~43295~1
- 42 C SOFT s t 0 0 0 4 1 0 1 |XIANSHI:20|~43296~1
(30) 37 C SOFT s t 0 0 0 5 1 1 0 |XIANSHI:20|~43299~1
- 28 B SOFT s t 0 0 0 1 1 1 0 |XIANSHI:20|~43300~1
(59) 86 F SOFT s t 0 0 0 5 0 1 0 |XIANSHI:20|~43302~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl文档\矩阵键盘\gyima.rpt
gyima
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
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