gyima.rpt

利用FPGA编写的键盘译码程序

Project Information                             d:\vhdl文档\矩阵键盘\gyima.rpt

MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 06/25/2008 01:01:31

Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

gyima     EPM7096LC68-7    21       8        0      87      79          90 %
gyima1    EPM7096LC68-7    13       32       0      95      15          98 %
gyima2    EPM7096LC68-7    26       12       0      96      0           100%
gyima3    EPM7096LC68-7    30       17       0      96      15          100%
gyima4    EPM7064LC44-7    17       17       0      63      0           98 %

TOTAL:                     107      86       0      437     109         97 %

User Pins:                 7        19       0  



Project Information                             d:\vhdl文档\矩阵键盘\gyima.rpt

** PROJECT COMPILATION MESSAGES **

Error: Project does not fit in specified device(s)
Info: Trying to find new partition/fit after discarding assignments as requested with the Partitioner/Fitter Status dialog box


Project Information                             d:\vhdl文档\矩阵键盘\gyima.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'CLK' chosen for auto global Clock


Project Information                             d:\vhdl文档\矩阵键盘\gyima.rpt

** MULTIPLE PIN CONNECTIONS **


Connect: {gyima1@30,    gyima4@6,     gyima2@37,    gyima3@12,    gyima@39}

Connect: {gyima1@24,    gyima4@24,    gyima2@25,    gyima3@67,    gyima@10}

Connect: {gyima1@27,    gyima4@4,     gyima2@27,    gyima3@9,     gyima@9}

Connect: {gyima1@25,    gyima4@44,    gyima2@28,    gyima3@54,    gyima@8}

Connect: {gyima1@13,    gyima3@17,    gyima2@14,    gyima@22}

Connect: {gyima1@18,    gyima4@40,    gyima@13}

Connect: {gyima1@14,    gyima4@43,    gyima@32}

Connect: {gyima1@15,    gyima4@9,     gyima@4}

Connect: {gyima1@17,    gyima4@26,    gyima@1}

Connect: {gyima1@23,    gyima4@38,    gyima@7}

Connect: {gyima3@46,    gyima2@24,    gyima1@42,    gyima@15}

Connect: {gyima2@56,    gyima4@27,    gyima@17}

Connect: {gyima4@14,    gyima2@57,    gyima@18}

Connect: {gyima@23,     gyima2@45,    gyima4@33}

Connect: {gyima1@50,    gyima2@29,    gyima@19}

Connect: {gyima4@39,    gyima2@32,    gyima@14}

Connect: {gyima4@13,    gyima@36}

Connect: {gyima4@21,    gyima@30}

Connect: {gyima1@54,    gyima3@15,    gyima2@36,    gyima@20}

Connect: {gyima4@16,    gyima2@46,    gyima@28}

Connect: {gyima@55,     gyima1@49}

Connect: {gyima4@19,    gyima2@51,    gyima@25}

Connect: {gyima4@37,    gyima@24}

Connect: {gyima4@20,    gyima2@52}

Connect: {gyima4@11,    gyima3@18}

Connect: {gyima1@51,    gyima4@32}

Connect: {gyima1@33,    gyima3@5}

Connect: {gyima1@46,    gyima3@62}

Connect: {gyima1@29,    gyima3@13}

Connect: {gyima1@7,     gyima3@22}

Connect: {gyima1@28,    gyima3@23}

Connect: {gyima1@32,    gyima3@7}

Connect: {gyima4@28,    gyima2@33}

Connect: {gyima4@18,    gyima1@60,    gyima3@44,    gyima2@7}

Connect: {gyima4@8,     gyima2@42}

Connect: {gyima4@12,    gyima3@33}

Connect: {gyima4@17,    gyima3@30}

Connect: {gyima3@24,    gyima4@34}

Connect: {gyima1@12,    gyima3@20}

Connect: {gyima2@65,    gyima3@29}

Connect: {gyima1@9,     gyima3@19}

Connect: {gyima2@8,     gyima3@32}

Connect: {gyima1@8,     gyima4@36,    gyima2@41}

Connect: {gyima4@41,    gyima2@44}

Connect: {gyima3@8,     gyima4@1}

Connect: {gyima1@4,     gyima3@45}

Connect: {gyima2@10,    gyima3@42}

Connect: {gyima3@61,    gyima2@23}

Connect: {gyima2@12,    gyima1@19}

Connect: {gyima3@52,    gyima2@22}

Connect: {gyima1@40,    gyima3@37}

Connect: {gyima1@10,    gyima3@25}

Connect: {gyima2@13,    gyima3@40}

Connect: {gyima3@51,    gyima2@20}

Connect: {gyima2@4,     gyima3@41}

Connect: {gyima1@5,     gyima2@54}

Connect: {gyima3@56,    gyima1@20}

Connect: {gyima2@5,     gyima1@56}

Connect: {gyima3@47,    gyima2@18}

Connect: {gyima1@22,    gyima3@36}

Connect: {gyima2@9,     gyima3@27}

Connect: {gyima4@7,     gyima2@17}

Connect: {gyima3@65,    gyima4@31}

Connect: {gyima4@5,     gyima3@28}

Connect: {gyima3@55,    gyima4@29}

Connect: {gyima2@40,    gyima3@39}

Connect: {gyima3@14,    gyima2@15}


Project Information                             d:\vhdl文档\矩阵键盘\gyima.rpt

** FILE HIERARCHY **



|cnt:1|
|cnt:1|lpm_add_sub:22|
|cnt:1|lpm_add_sub:22|addcore:adder|
|cnt:1|lpm_add_sub:22|addcore:adder|addcore:adder0|
|cnt:1|lpm_add_sub:22|altshift:result_ext_latency_ffs|
|cnt:1|lpm_add_sub:22|altshift:carry_ext_latency_ffs|
|cnt:1|lpm_add_sub:22|altshift:oflow_ext_latency_ffs|
|dclk:2|
|dclk:2|lpm_add_sub:17|
|dclk:2|lpm_add_sub:17|addcore:adder|
|dclk:2|lpm_add_sub:17|addcore:adder|addcore:adder0|
|dclk:2|lpm_add_sub:17|altshift:result_ext_latency_ffs|
|dclk:2|lpm_add_sub:17|altshift:carry_ext_latency_ffs|
|dclk:2|lpm_add_sub:17|altshift:oflow_ext_latency_ffs|
|yima:3|
|addbcd:14|
|addbcd:14|lpm_add_sub:61|
|addbcd:14|lpm_add_sub:61|addcore:adder|
|addbcd:14|lpm_add_sub:61|addcore:adder|addcore:adder0|
|addbcd:14|lpm_add_sub:61|altshift:result_ext_latency_ffs|
|addbcd:14|lpm_add_sub:61|altshift:carry_ext_latency_ffs|
|addbcd:14|lpm_add_sub:61|altshift:oflow_ext_latency_ffs|
|addbcd:14|lpm_add_sub:232|
|addbcd:14|lpm_add_sub:232|addcore:adder|
|addbcd:14|lpm_add_sub:232|addcore:adder|addcore:adder0|
|addbcd:14|lpm_add_sub:232|altshift:result_ext_latency_ffs|
|addbcd:14|lpm_add_sub:232|altshift:carry_ext_latency_ffs|
|addbcd:14|lpm_add_sub:232|altshift:oflow_ext_latency_ffs|
|jia:15|
|xianshi:20|
|cnta:22|
|cnta:22|lpm_add_sub:28|
|cnta:22|lpm_add_sub:28|addcore:adder|
|cnta:22|lpm_add_sub:28|addcore:adder|addcore:adder0|
|cnta:22|lpm_add_sub:28|altshift:result_ext_latency_ffs|
|cnta:22|lpm_add_sub:28|altshift:carry_ext_latency_ffs|
|cnta:22|lpm_add_sub:28|altshift:oflow_ext_latency_ffs|
|cnta:22|lpm_add_sub:63|
|cnta:22|lpm_add_sub:63|addcore:adder|
|cnta:22|lpm_add_sub:63|addcore:adder|addcore:adder0|
|cnta:22|lpm_add_sub:63|altshift:result_ext_latency_ffs|
|cnta:22|lpm_add_sub:63|altshift:carry_ext_latency_ffs|
|cnta:22|lpm_add_sub:63|altshift:oflow_ext_latency_ffs|


Device-Specific Information:                    d:\vhdl文档\矩阵键盘\gyima.rpt
gyima

***** Logic for device 'gyima' compiled without errors.




Device: EPM7096LC68-7

Device Options: