📄 addbcd.rpt
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Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC24 |LPM_ADD_SUB:61|addcore:adder|addcore:adder0|gcp2
| +----------------------------- LC25 |LPM_ADD_SUB:61|addcore:adder|addcore:adder0|g4
| | +--------------------------- LC29 |LPM_ADD_SUB:61|addcore:adder|addcore:adder0|result_node0
| | | +------------------------- LC27 |LPM_ADD_SUB:61|addcore:adder|addcore:adder0|result_node2
| | | | +----------------------- LC30 |LPM_ADD_SUB:61|addcore:adder|addcore:adder0|result_node3
| | | | | +--------------------- LC31 |LPM_ADD_SUB:232|addcore:adder|addcore:adder0|g4
| | | | | | +------------------- LC32 |LPM_ADD_SUB:232|addcore:adder|addcore:adder0|result_node3
| | | | | | | +----------------- LC26 |LPM_ADD_SUB:232|addcore:adder|addcore:adder0|result_node4
| | | | | | | | +--------------- LC28 outnum1
| | | | | | | | | +------------- LC23 outnum2
| | | | | | | | | | +----------- LC22 outnum3
| | | | | | | | | | | +--------- LC21 outnum4
| | | | | | | | | | | | +------- LC17 q34
| | | | | | | | | | | | | +----- LC18 q33
| | | | | | | | | | | | | | +--- LC19 q32
| | | | | | | | | | | | | | | +- LC20 q31
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC24 -> - - - - * - - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:61|addcore:adder|addcore:adder0|gcp2
LC25 -> - - - - - - - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:61|addcore:adder|addcore:adder0|g4
LC27 -> - - - - - - - - - - - - - - * - | - * | <-- |LPM_ADD_SUB:61|addcore:adder|addcore:adder0|result_node2
LC30 -> - - - - - - - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:61|addcore:adder|addcore:adder0|result_node3
LC31 -> - - - - - - - * - - - - - - - - | - * | <-- |LPM_ADD_SUB:232|addcore:adder|addcore:adder0|g4
LC32 -> - - - - - - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:232|addcore:adder|addcore:adder0|result_node3
LC26 -> - - - - - - - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:232|addcore:adder|addcore:adder0|result_node4
LC17 -> - - - - - - - * * * * * * - - - | - * | <-- q34
LC18 -> - - - - - * * - * * * * - * - - | - * | <-- q33
LC19 -> - - - - - * * - * * * * - - * - | - * | <-- q32
LC20 -> - - - - - * * - * * * * - - - * | - * | <-- q31
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk
13 -> * * * * - - - - - - - - - - - * | - * | <-- num10
12 -> * * - * - - - - - - - - - - - * | - * | <-- num11
11 -> * * - * - - - - - - - - - - - - | - * | <-- num12
9 -> - * - - * - - - - - - - - - - - | - * | <-- num13
8 -> * * * * - - - - - - - - - - - * | - * | <-- num20
7 -> * * - * - - - - - - - - - - - * | - * | <-- num21
6 -> * * - * - - - - - - - - - - - - | - * | <-- num22
5 -> - * - - * - - - - - - - - - - - | - * | <-- num23
4 -> - - - - - - - - - - - - * * * * | * * | <-- start
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl文档\矩阵键盘\addbcd.rpt
addbcd
** EQUATIONS **
clk : INPUT;
num10 : INPUT;
num11 : INPUT;
num12 : INPUT;
num13 : INPUT;
num20 : INPUT;
num21 : INPUT;
num22 : INPUT;
num23 : INPUT;
start : INPUT;
-- Node name is 'outnum0' = 'q0'
-- Equation name is 'outnum0', location is LC013, type is output.
outnum0 = DFFE( q30 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'outnum1' = 'q1~41'
-- Equation name is 'outnum1', location is LC028, type is output.
outnum1 = DFFE( _EQ001 $ !q31, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !q31 & !q32 & q33 & !q34
# !q33 & !q34;
-- Node name is 'outnum2' = 'q2~41'
-- Equation name is 'outnum2', location is LC023, type is output.
outnum2 = DFFE( _EQ002 $ q32, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !q31 & q32 & q33
# !q31 & q34;
-- Node name is 'outnum3' = 'q3~41'
-- Equation name is 'outnum3', location is LC022, type is output.
outnum3 = DFFE( _EQ003 $ _LC032, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !_LC032 & !q31 & !q32 & q33 & !q34
# _LC032 & !q33 & !q34;
-- Node name is 'outnum4' = 'q4'
-- Equation name is 'outnum4', location is LC021, type is output.
outnum4 = DFFE( _EQ004 $ _LC026, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC026 & !q31 & !q32 & !q34
# _LC026 & !q33 & !q34;
-- Node name is 'outnum5'
-- Equation name is 'outnum5', location is LC010, type is output.
outnum5 = LCELL( GND $ GND);
-- Node name is 'outnum6'
-- Equation name is 'outnum6', location is LC011, type is output.
outnum6 = LCELL( GND $ GND);
-- Node name is 'outnum7'
-- Equation name is 'outnum7', location is LC012, type is output.
outnum7 = LCELL( GND $ GND);
-- Node name is ':31' = 'q30'
-- Equation name is 'q30', location is LC004, type is buried.
q30 = DFFE( _EQ005 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC029 & start
# q30 & !start;
-- Node name is ':30' = 'q31'
-- Equation name is 'q31', location is LC020, type is buried.
q31 = DFFE( _EQ006 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = num10 & num11 & num20 & num21 & start
# num10 & !num11 & num20 & !num21 & start
# !num10 & start & _X001 & _X002
# !num20 & start & _X001 & _X002
# q31 & !start;
_X001 = EXP( num11 & num21);
_X002 = EXP(!num11 & !num21);
-- Node name is ':29' = 'q32'
-- Equation name is 'q32', location is LC019, type is buried.
q32 = DFFE( _EQ007 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC027 & start
# q32 & !start;
-- Node name is ':28' = 'q33'
-- Equation name is 'q33', location is LC018, type is buried.
q33 = DFFE( _EQ008 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC030 & start
# q33 & !start;
-- Node name is ':27' = 'q34'
-- Equation name is 'q34', location is LC017, type is buried.
q34 = DFFE( _EQ009 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = _LC025 & start
# q34 & !start;
-- Node name is '|LPM_ADD_SUB:61|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC024', type is buried
_LC024 = LCELL( _EQ010 $ GND);
_EQ010 = num10 & num20 & _X002 & _X003
# num11 & num21 & _X003
# num12 & num22;
_X002 = EXP(!num11 & !num21);
_X003 = EXP(!num12 & !num22);
-- Node name is '|LPM_ADD_SUB:61|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( _EQ011 $ _EQ012);
_EQ011 = num10 & num20 & _X002 & _X003 & _X004 & _X005
# num11 & num21 & _X003 & _X004 & _X005
# num12 & num22 & _X004 & _X005;
_X002 = EXP(!num11 & !num21);
_X003 = EXP(!num12 & !num22);
_X004 = EXP(!num13 & !num23);
_X005 = EXP( num13 & num23);
_EQ012 = num13 & num23;
-- Node name is '|LPM_ADD_SUB:61|addcore:adder|addcore:adder0|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried
_LC029 = LCELL( num20 $ num10);
-- Node name is '|LPM_ADD_SUB:61|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried
_LC027 = LCELL( _EQ013 $ _EQ014);
_EQ013 = num10 & num20 & _X002
# num11 & num21;
_X002 = EXP(!num11 & !num21);
_EQ014 = _X003 & _X006;
_X003 = EXP(!num12 & !num22);
_X006 = EXP( num12 & num22);
-- Node name is '|LPM_ADD_SUB:61|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC030', type is buried
_LC030 = LCELL( _EQ015 $ _LC024);
_EQ015 = _X004 & _X005;
_X004 = EXP(!num13 & !num23);
_X005 = EXP( num13 & num23);
-- Node name is '|LPM_ADD_SUB:232|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( _EQ016 $ q33);
_EQ016 = !q31 & !q32 & q33;
-- Node name is '|LPM_ADD_SUB:232|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC032', type is buried
_LC032 = LCELL(!q33 $ _EQ017);
_EQ017 = !q31 & !q32;
-- Node name is '|LPM_ADD_SUB:232|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried
_LC026 = LCELL( q34 $ _LC031);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\vhdl文档\矩阵键盘\addbcd.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,625K
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