cnta.vhd

利用FPGA编写的键盘译码程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cnta is
port(clk: in std_logic; 
       q: out std_logic_vector(3 downto 0));
end cnta;

architecture cnt_arc of cnta is
begin
process(clk)	
variable tmp:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
	if tmp="1111" then
		 tmp:="0000";
    else
	     tmp:=tmp+1;
	end if;
end if;
q<=tmp-1;
end process;
end cnt_arc;