jia.vhd

来自「利用FPGA编写的键盘译码程序」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity jia is
  port(   clk,a : in std_logic;
            int : in std_logic_vector(3 downto 0);
       out1,out2: out std_logic_vector(3 downto 0) 
       );
end jia;

architecture rt1 of jia is
signal s1,s2 : std_logic_vector(3 downto 0);
begin
  process(clk,a)
   begin
    if clk'event and clk='1' then
       if(a='0') then
          s1<=int;
          s2<=s2;
       else 
          s1<=s1;
          s2<=int;
       end if;
    end if;
 end process;
 out1<=s1;
 out2<=s2;
end rt1;